Andrzej J Strojwas (48 results)
- Hardcover
Seller: Bay State Book Company, North Smithfield, RI, U.S.A.Bay State Book Company
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£ 36.52
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Condition: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Language: English
Published by Kluwer Academic Publishers, Dordrecht, Holland, 1997
- Hardcover
- First Edition
Seller: PsychoBabel & Skoob Books, Didcot, United KingdomPsychoBabel & Skoob Books
Contact seller5-star sellerCondition: Used - Very good
£ 26.75
£ 12.50 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
hardcover. Condition: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
- Softcover
Seller: Hamelyn, Madrid, M, SpainHamelyn
Contact seller5-star sellerCondition: Used - Very good
£ 35.47
£ 11.10 shippingShips from Spain to U.S.A.Quantity: 1 available
Condition: Bueno. : Este libro trata sobre el diseño VLSI para la fabricación y la mejora del rendimiento. Cubre temas de ingeniería de sistemas e ingeniería informática. Es un recurso en línea que también está disponible en forma impresa. El libro forma parte de 'The Kluwer International Series in Engineering and Computer Scien…ce'. EAN: 9781461288169 Tipo: Libros Categoría: Tecnología|Ciencias Título: VLSI Design for Manufacturing: Yield Enhancement Autor: Stephen W. Director| Wojciech Maly| Andrzej J. Strojwas Editorial: Springer US Idioma: en Páginas: 308 Formato: Tapa blanda.
Vlsi Design for Manufacturing: Yield Enhancement
Director, Stephen W., With Wojciech Maly And Andrzej J. Strojwas
- Hardcover
Seller: BookDepart, Shepherdstown, WV, U.S.A.BookDepart
Contact seller5-star sellerCondition: Used - Very good
£ 49.59
£ 6.24 shippingShips within U.S.A.Quantity: 1 available
Hardcover. Condition: Very Good. Hardcover; fading and light shelf wear to exterior; light fading to page ed ges; otherwise in very good condition with clean text, firm binding.
- Hardcover
Seller: CONTINENTAL MEDIA & BEYOND, Ocala, FL, U.S.A.CONTINENTAL MEDIA & BEYOND
Contact seller5-star sellerCondition: Used - Very good
£ 60.88
£ 5.17 shippingShips within U.S.A.Quantity: 1 available
Condition: Used: Very Good. 1990 hardcover no dust jacket as issued volume 86 Name in book clean unmarked pages Published by Kluwer Academic 291 pages M-14.
- Hardcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
Contact seller4-star sellerCondition: Used - As new
£ 47.00
£ 25.00 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Hardcover. Condition: Like New. Like NewLIKE NEW. book.
- Softcover
Seller: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contact seller5-star sellerCondition: New
£ 84.10
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Condition: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Hardcover
Seller: Basi6 International, Irving, TX, U.S.A.Basi6 International
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£ 84.10
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Condition: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Seller: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.Goodwill of Silicon Valley
Contact seller5-star sellerCondition: Used - Good
£ 82.74
£ 2.95 shippingShips within U.S.A.Quantity: 1 available
Condition: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
- Hardcover
Seller: -OnTimeBooks-, Phoenix, AZ, U.S.A.-OnTimeBooks-
Contact seller5-star sellerCondition: Used - Good
£ 88.13
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Condition: good. A copy that has been read, remains in good condition. All pages are intact, and the cover is intact. The spine and cover show signs of wear. Pages can include notes and highlighting and show signs of wear, and the copy can include "From the library of" labels or previous owner inscriptions. 100% GUARANTEE! Shipp…ed with delivery confirmation, if you're not satisfied with purchase please return item! Ships via media mail.
- Hardcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
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£ 97.09
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Condition: New.
- Hardcover
Seller: BennettBooksLtd, Los Angeles, CA, U.S.A.BennettBooksLtd
Contact seller5-star sellerCondition: New
£ 93.82
£ 5.14 shippingShips within U.S.A.Quantity: 1 available
hardcover. Condition: New. In shrink wrap. Looks like an interesting title.
- Hardcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contact seller5-star sellerCondition: Used - As new
£ 104.99
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Condition: As New. Unread book in perfect condition.
- Softcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
£ 96.88
£ 11.98 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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£ 96.88
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Condition: New. In.
- Hardcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
Contact seller5-star sellerCondition: New
£ 96.87
£ 15.00 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New.
VLSI Design for Manufacturing: Yield Enhancement
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Seller: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contact seller5-star sellerCondition: New
£ 116.45
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Condition: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Hardcover
Seller: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contact seller5-star sellerCondition: New
£ 116.45
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Condition: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Hardcover
Seller: Buchpark, Trebbin, GermanyBuchpark
Contact seller5-star sellerCondition: Used - Very good
£ 31.36
£ 89.76 shippingShips from Germany to U.S.A.Quantity: 1 available
Condition: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-…fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Hardcover
Seller: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrelandKennys Bookshop and Art Galleries Ltd.
Contact seller5-star sellerCondition: New
£ 116.75
£ 8.12 shippingShips from Ireland to U.S.A.Quantity: 15 available
Condition: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
- Hardcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
Contact seller5-star sellerCondition: Used - As new
£ 107.51
£ 15.00 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: As New. Unread book in perfect condition.
- Hardcover
Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
Contact seller4-star sellerCondition: New
£ 122.87
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Condition: New. pp. 176.
- Hardcover
Seller: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
Contact seller5-star sellerCondition: New
£ 141.68
£ 7.76 shippingShips within U.S.A.Quantity: 15 available
Condition: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
£ 137.84
£ 11.98 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
£ 137.84
£ 11.98 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Seller: California Books, Miami, FL, U.S.A.California Books
Contact seller4-star sellerCondition: New
£ 153.75
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Condition: New.
- Hardcover
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
Contact seller5-star sellerCondition: New
£ 99.29
£ 53.15 shippingShips from Germany to U.S.A.Quantity: 1 available
Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (p…re-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Softcover
Seller: Buchpark, Trebbin, GermanyBuchpark
Contact seller5-star sellerCondition: Used - Fine
£ 71.48
£ 89.76 shippingShips from Germany to U.S.A.Quantity: 1 available
Condition: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Researc…h in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Softcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
Contact seller4-star sellerCondition: Used - As new
£ 152.00
£ 25.00 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Hardcover
Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
Contact seller4-star sellerCondition: New
£ 180.09
£ 2.95 shippingShips within U.S.A.Quantity: 4 available
Condition: New. pp. 308.
