Joseph Anthony Prathap (14 results)
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Seller: California Books, Miami, FL, U.S.A.California Books
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Taschenbuch. Condition: Neu. Design of Proposed Hybrid 128-bit Parallel Adder/Subtractor | Joseph Anthony Prathap | Taschenbuch | Englisch | 2020 | LAP LAMBERT Academic Publishing | EAN 9786202923682 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbie…ter: preigu.
Language: English
Published by LAP LAMBERT Academic Publishing Okt 2020, 2020
- Softcover
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 72 pp. Englisch.
Language: English
Published by LAP LAMBERT Academic Publishing Okt 2020, 2020
- Softcover
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The proposed FPGA based 64-bit RISC Communication Processor (RCP) design for developing the processor with 32 operations using pipeline feature is an efficient technique in which basic processor operations like arithmetic and logica…l unit, shifting unit, comparator unit based. And a special communication unit which has signal generation and transmission operations and application unit which consist of traffic light, digital clock generation and LFSR (linear feedback Shift Register) operations are been incorporated into the design of RCP. The RCP design is implemented using Virtex 7 using Verilog HDL and is compared with other FPGA members like Spartan 3E and Spartan 3A DSP. 68 pp. Englisch.
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- Softcover
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Seller: Biblios, frankfurt am main, HESSE, GermanyBiblios
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- Softcover
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Seller: moluna, Greven, Germanymoluna
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: PRATHAP JOSEPH ANTHONYDr.Joseph Anthony Prathap was born in 1981 in Puducherry. He has obtained B.E [Electronics and Communication] and M.Tech [VLSI Design] degrees in 2003 and 2007 respectively from Sa…thyabama University. He has put.
Language: English
Published by LAP LAMBERT Academic Publishing Okt 2020, 2020
- Softcover
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The book explains about the transistor level design of novel parallel adder/subtractor using the 45 nm technology in cadence tool. The proposed novel parallel 128-bit Adder/Subtractor is utilized in the design of parallel adder/ subtrac…tor with the resolution up to 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Parallel Adder/Subtractor. This paper compares the parametric values of power, delay, and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed parallel design exhibits low power and delay as the resolution of the design is increased. Also, the chip area is 0.3138µm2 for the 28T PAS circuit and 0.165 µm2 for the proposed 24T PAS circuitVDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 72 pp. Englisch.
Language: English
Published by LAP LAMBERT Academic Publishing Okt 2020, 2020
- Softcover
- Print on Demand
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The proposed FPGA based 64-bit RISC Communication Processor (RCP) design for developing the processor with 32 operations using pipeline feature is an efficient technique in which basic processor operations like arithmetic and logical un…it, shifting unit, comparator unit based. And a special communication unit which has signal generation and transmission operations and application unit which consist of traffic light, digital clock generation and LFSR (linear feedback Shift Register) operations are been incorporated into the design of RCP. The RCP design is implemented using Virtex 7 using Verilog HDL and is compared with other FPGA members like Spartan 3E and Spartan 3A DSP.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch.
- Softcover
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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The proposed FPGA based 64-bit RISC Communication Processor (RCP) design for developing the processor with 32 operations using pipeline feature is an efficient technique in which basic processor operations like arithmetic and logical uni…t, shifting unit, comparator unit based. And a special communication unit which has signal generation and transmission operations and application unit which consist of traffic light, digital clock generation and LFSR (linear feedback Shift Register) operations are been incorporated into the design of RCP. The RCP design is implemented using Virtex 7 using Verilog HDL and is compared with other FPGA members like Spartan 3E and Spartan 3A DSP.
- Softcover
- Print on Demand
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The book explains about the transistor level design of novel parallel adder/subtractor using the 45 nm technology in cadence tool. The proposed novel parallel 128-bit Adder/Subtractor is utilized in the design of parallel adder/ subtract…or with the resolution up to 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Parallel Adder/Subtractor. This paper compares the parametric values of power, delay, and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed parallel design exhibits low power and delay as the resolution of the design is increased. Also, the chip area is 0.3138µm2 for the 28T PAS circuit and 0.165 µm2 for the proposed 24T PAS circuit.
