Design of Proposed Hybrid 128-bit Parallel Adder/Subtractor - Softcover

Prathap, Joseph Anthony

Softcover

ISBN 10: 6202923687 ISBN 13: 9786202923682

Publisher: LAP Lambert Academic Publishing, 2020

Synopsis

The book explains about the transistor level design of novel parallel adder/subtractor using the 45 nm technology in cadence tool. The proposed novel parallel 128-bit Adder/Subtractor is utilized in the design of parallel adder/ subtractor with the resolution up to 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Parallel Adder/Subtractor. This paper compares the parametric values of power, delay, and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed parallel design exhibits low power and delay as the resolution of the design is increased. Also, the chip area is 0.3138µm2 for the 28T PAS circuit and 0.165 µm2 for the proposed 24T PAS circuit

Edition details

• Publisher: LAP Lambert Academic Publishing
• Publication date: 2020
• Language: English
• ISBN 10: 6202923687
• ISBN 13: 9786202923682
• Binding: Paperback
• Number of pages: 72