Chatterjee Sulagna (8 results)
- Softcover
Seller: California Books, Miami, FL, U.S.A.California Books
Contact seller4-star sellerCondition: New
£ 67.29
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Condition: New.
- Softcover
Seller: preigu, Osnabrück, Germanypreigu
Contact seller5-star sellerCondition: New
£ 52.10
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Taschenbuch. Condition: Neu. Nanoscale Strain-engineering in Solid State Semiconductor Devices | From Fundamentals to Applications | Sulagna Chatterjee | Taschenbuch | Englisch | 2026 | LAP LAMBERT Academic Publishing | EAN 9786209522390 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 R…IGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.
- Softcover
- Print on Demand
Seller: PBShop.store US, Wood Dale, IL, U.S.A.PBShop.store US
Contact seller5-star sellerCondition: New
£ 71.98
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PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
- Softcover
- Print on Demand
Seller: PBShop.store UK, Fairford, GLOS, United KingdomPBShop.store UK
Contact seller5-star sellerCondition: New
£ 67.07
£ 3.29 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
Language: English
Published by LAP LAMBERT Academic Publishing Feb 2026 2026
- Softcover
- Print on Demand
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
Contact seller5-star sellerCondition: New
£ 61.21
£ 19.84 shippingShips from Germany to U.S.A.Quantity: 2 available
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 136 pp. Englisch.
- Softcover
- Print on Demand
Seller: CitiRetail, Stevenage, United KingdomCitiRetail
Contact seller5-star sellerCondition: New
£ 71.99
£ 37.00 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Paperback. Condition: new. Paperback. An analytical model has been developed that estimates induced stress in horizontally embedded nanowires. Stress has been considered to be induced due to mismatch of both lattice and thermo-elastic constants. The contribution of both process- and substrate-induced stress has been accounted fo…r. Various materials have been chosen as substrate for different nanowire materials, depending on their crystal structures. The magnitude and nature of induced stress has been engineered by varying the fractional insertion of the nanowire into the substrate. Nanowires being extremely petite structures always need to be mounted on some substrate. Hence, a commercial substrate has been proposed, such that mobility enhancement through stress-engineering might be accomplished by varying the fractional insertion. Step-by-step stress-engineering for partially embedded nanowire FETs has been performed. The choice of high-k gate dielectric has been shown to play an important role. Similar stress-engineering has been performed for UTB MOSFETs and FinFETs. Both such FETs have been proposed to be fabricated on ingenious, commercial IOS substrates, capable of inducing stress of desired nature and magnitude. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.
Language: English
Published by LAP LAMBERT Academic Publishing Feb 2026 2026
- Softcover
- Print on Demand
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
Contact seller5-star sellerCondition: New
£ 61.21
£ 51.75 shippingShips from Germany to U.S.A.Quantity: 1 available
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -An analytical model has been developed that estimates induced stress in horizontally embedded nanowires. Stress has been considered to be induced due to mismatch of both lattice and thermo-elastic constants. The contribution of both pro…cess- and substrate-induced stress has been accounted for. Various materials have been chosen as substrate for different nanowire materials, depending on their crystal structures. The magnitude and nature of induced stress has been engineered by varying the fractional insertion of the nanowire into the substrate. Nanowires being extremely petite structures always need to be mounted on some substrate. Hence, a commercial substrate has been proposed, such that mobility enhancement through stress-engineering might be accomplished by varying the fractional insertion. Step-by-step stress-engineering for partially embedded nanowire FETs has been performed. The choice of high-k gate dielectric has been shown to play an important role. Similar stress-engineering has been performed for UTB MOSFETs and FinFETs. Both such FETs have been proposed to be fabricated on ingenious, commercial IOS substrates, capable of inducing stress of desired nature and magnitude.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 136 pp. Englisch.
- Softcover
- Print on Demand
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
Contact seller5-star sellerCondition: New
£ 61.94
£ 52.71 shippingShips from Germany to U.S.A.Quantity: 2 available
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering.
