Nanoscale Strain-engineering in Solid State Semiconductor Devices

Language: English

Published by LAP LAMBERT Academic Publishing Feb 2026, 2026

6209522394 / 9786209522390

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This item is printed on demand - Print on Demand Titel. Neuware -An analytical model has been developed that estimates induced stress in horizontally embedded nanowires. Stress has been considered to be induced due to mismatch of both lattice and thermo-elastic constants. The contribution of both process- and substrate-induced stress has been accounted for. Various materials have been chosen as substrate for different nanowire materials, depending on their crystal structures. The magnitude and nature of induced stress has been engineered by varying the fractional insertion of the nanowire into the substrate. Nanowires being extremely petite structures always need to be mounted on some substrate. Hence, a commercial substrate has been proposed, such that mobility enhancement through stress-engineering might be accomplished by varying the fractional insertion. Step-by-step stress-engineering for partially embedded nanowire FETs has been performed. The choice of high-k gate dielectric has been shown to play an important role. Similar stress-engineering has been performed for UTB MOSFETs and FinFETs. Both such FETs have been proposed to be fabricated on ingenious, commercial IOS substrates, capable of inducing stress of desired nature and magnitude.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 136 pp. Englisch.…

Seller Inventory # 9786209522390

Title
Nanoscale Strain-engineering in Solid State Semiconductor Devices
Author
Sulagna Chatterjee
Publisher
LAP LAMBERT Academic Publishing Feb 2026
Publication year
2026
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6209522394
ISBN 13
9786209522390
Item weight
221 grams
Dimensions
220x150x9 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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