Nanoscale Strain-engineering in Solid State Semiconductor Devices (Paperback)

Language: English

Published by LAP Lambert Academic Publishing, 2026

6209522394 / 9786209522390

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Paperback. An analytical model has been developed that estimates induced stress in horizontally embedded nanowires. Stress has been considered to be induced due to mismatch of both lattice and thermo-elastic constants. The contribution of both process- and substrate-induced stress has been accounted for. Various materials have been chosen as substrate for different nanowire materials, depending on their crystal structures. The magnitude and nature of induced stress has been engineered by varying the fractional insertion of the nanowire into the substrate. Nanowires being extremely petite structures always need to be mounted on some substrate. Hence, a commercial substrate has been proposed, such that mobility enhancement through stress-engineering might be accomplished by varying the fractional insertion. Step-by-step stress-engineering for partially embedded nanowire FETs has been performed. The choice of high-k gate dielectric has been shown to play an important role. Similar stress-engineering has been performed for UTB MOSFETs and FinFETs. Both such FETs have been proposed to be fabricated on ingenious, commercial IOS substrates, capable of inducing stress of desired nature and magnitude. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.…

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Title
Nanoscale Strain-engineering in Solid State Semiconductor Devices (Paperback)
Author
Sulagna Chatterjee
Publisher
LAP Lambert Academic Publishing
Publication year
2026
Condition
new
Binding
Paperback
Language
English
ISBN 10
6209522394
ISBN 13
9786209522390

CitiRetail

Stevenage, United Kingdom

5-star seller

AbeBooks seller since June 29, 2022

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