Study Analysis Vedic Multipler by Baishnab Krishna (6 results)

Taschenbuch. Condition: Neu. Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit | Krishna Lal Baishnab (u. a.) | Taschenbuch | 92 S. | Englisch | 2014 | LAP LAMBERT Academic Publishing | EAN 9783659613920 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier. 92 pp. Englisch.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Baishnab Krishna LalDr K.L.Baishnab obtained his BE from (Regional Enginnering College Silchar) (presently National Institute of Technology Silchar INDIA) in the year 1995. M.Tech from Indian Institute of Technology kharagpur (INDIA).

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 92 pp. Englisch.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.