Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit - Softcover

Baishnab, Krishna Lal; Kumar, Ram; Gupta, Radhe Shyam

Softcover

ISBN 10: 3659613924 ISBN 13: 9783659613920

Publisher: LAP LAMBERT Academic Publishing, 2014

Synopsis

This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.

About this title

About the Author

Dr K.L.Baishnab obtained his BE from (Regional Enginnering College Silchar) (presently National Institute of Technology Silchar INDIA) in the year 1995. M.Tech from Indian Institute of Technology kharagpur (INDIA) in the year 2004. PhD from NIT Silchar 2013.He is currently working as a Asst professor in ECE dept NIT Silchar (INDIA).

Edition details

• Publisher: LAP LAMBERT Academic Publishing
• Publication date: 2014
• ISBN 10: 3659613924
• ISBN 13: 9783659613920
• Binding: Paperback
• Language: English
• Number of pages: 92