Quantum Key Distribution Using by Jumaa Noor (16 results)
- Softcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
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- Softcover
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- Softcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
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- Softcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
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More images- Softcover
Seller: preigu, Osnabrück, Germanypreigu
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Taschenbuch. Condition: Neu. Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis | Noor Kareem Jumaa (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2021 | Noor Publishing | EAN 9786204720067 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osn…abrück, mail[at]preigu[dot]de | Anbieter: preigu.
- Softcover
- Print on Demand
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PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
- Softcover
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PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
- Softcover
- Print on Demand
Seller: Majestic Books, Hounslow, United KingdomMajestic Books
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- Softcover
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Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
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- Softcover
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correcti…on stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins. 100 pp. Englisch.
- Softcover
- Print on Demand
Seller: Biblios, frankfurt am main, HESSE, GermanyBiblios
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- Softcover
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Seller: moluna, Greven, Germanymoluna
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Jumaa Noor KareemNoor Kareem Jumaa was received her B.Sc degree in computer engineering from university of Baghdad, Iraq in 2010 and the M.Sc degree in quantum cryptography and data security from the de…partment of electronics and com.
- Softcover
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction s…tage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.Books on Demand GmbH, Überseering 33, 22297 Hamburg 100 pp. Englisch.
- Softcover
- Print on Demand
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction st…age are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.
