T Kalavathi Devi Sakthivel (30 results)
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Seller: Revaluation Books, Exeter, United KingdomRevaluation Books
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Paperback. Condition: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock.
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Taschenbuch. Condition: Neu. Low Power Asynchronous Logic design for Viterbi Decoders | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | 56 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139851294 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]pre…igu[dot]de | Anbieter: preigu.
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Taschenbuch. Condition: Neu. Conception de logique asynchrone à faible consommation pour les décodeurs de Viterbi | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | Französisch | 2023 | Editions Notre Savoir | EAN 9786205857229 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück…, mail[at]preigu[dot]de | Anbieter: preigu.
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Taschenbuch. Condition: Neu. Desenho de lógica assíncrona de baixa potência para descodificadores Viterbi | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | Portugiesisch | 2023 | Edições Nosso Conhecimento | EAN 9786205860137 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück,… mail[at]preigu[dot]de | Anbieter: preigu.
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Taschenbuch. Condition: Neu. Progettazione di logica asincrona a basso consumo per decodificatori Viterbi | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | Italienisch | 2023 | Edizioni Sapienza | EAN 9786205860120 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]pr…eigu[dot]de | Anbieter: preigu.
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Taschenbuch. Condition: Neu. Asynchroner Logikentwurf mit geringem Energieverbrauch für Viterbi-Dekoder | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | 56 S. | Deutsch | 2023 | Verlag Unser Wissen | EAN 9786205857236 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[a…t]preigu[dot]de | Anbieter: preigu.
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Language: English
Published by LAP LAMBERT Academic Publishing Sep 2018, 2018
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design.… Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. 56 pp. Englisch.
Language: Spanish
Published by Ediciones Nuestro Conocimiento Mrz 2023, 2023
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Este libro analiza el diseño de la lógica asíncrona y su importancia en el diseño digital. La mayoría de los descodificadores diseñados y fabricados hoy en día son síncronos. El problema de la desviación del reloj es un reto importa…nte en el diseño síncrono. Por otro lado, los sistemas asíncronos se están haciendo familiares, ya que no necesitan un reloj global y se sincronizan localmente mediante protocolos de comunicación. Se diseña una arquitectura VLSI asíncrona para un decodificador de Viterbi utilizando plantillas Quasi Delay Insensitive (QDI) y Lógica de Interruptor de Tensión en Cascada Diferencial (DCVSL). Se ofrece una visión general de la implementación asíncrona. 56 pp. Spanisch.
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviDr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published pa…pers in reputed journals and in.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Ce livre traite de la conception de la logique asynchrone et de son importance dans la conception numérique. La plupart des décodeurs conçus et fabriqués aujourd'hui sont synchrones. Le problème du décalage d'horloge est un défi maj…eur dans la conception synchrone. Par ailleurs, les systèmes asynchrones deviennent de plus en plus familiers, car ils n'ont pas besoin d'horloge globale et sont synchronisés localement au moyen de protocoles de communication. L'architecture VLSI asynchrone d'un décodeur de Viterbi est conçue à l'aide de modèles quasi insensibles au délai (QDI) et d'une logique de commutation de tension en cascade différentielle (DCVSL). Il donne un aperçu de la mise en oeuvre asynchrone. 56 pp. Französisch.
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Language: English
Published by LAP LAMBERT Academic Publishing Sep 2018, 2018
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alt…ernatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch.
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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alte…rnatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.
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Language: Spanish
Published by Ediciones Nuestro Conocimiento Mär 2023, 2023
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Este libro analiza el diseño de la lógica asíncrona y su importancia en el diseño digital. La mayoría de los descodificadores diseñados y fabricados hoy en día son síncronos. El problema de la desviación del reloj es un reto importante…en el diseño síncrono. Por otro lado, los sistemas asíncronos se están haciendo familiares, ya que no necesitan un reloj global y se sincronizan localmente mediante protocolos de comunicación. Se diseña una arquitectura VLSI asíncrona para un decodificador de Viterbi utilizando plantillas Quasi Delay Insensitive (QDI) y Lógica de Interruptor de Tensión en Cascada Diferencial (DCVSL). Se ofrece una visión general de la implementación asíncrona.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Spanisch.
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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Este libro analiza el diseño de la lógica asíncrona y su importancia en el diseño digital. La mayoría de los descodificadores diseñados y fabricados hoy en día son síncronos. El problema de la desviación del reloj es un reto importante e…n el diseño síncrono. Por otro lado, los sistemas asíncronos se están haciendo familiares, ya que no necesitan un reloj global y se sincronizan localmente mediante protocolos de comunicación. Se diseña una arquitectura VLSI asíncrona para un decodificador de Viterbi utilizando plantillas Quasi Delay Insensitive (QDI) y Lógica de Interruptor de Tensión en Cascada Diferencial (DCVSL). Se ofrece una visión general de la implementación asíncrona.
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Questo libro tratta la progettazione della logica asincrona e la sua importanza nella progettazione digitale. La maggior parte dei decodificatori progettati e realizzati oggi sono sincroni. Il problema del clock skew è una sfida imp…ortante nella progettazione sincrona. In alternativa, i sistemi asincroni stanno diventando familiari perché non hanno bisogno di un orologio globale, in quanto sono sincronizzati localmente per mezzo di protocolli di comunicazione. L'architettura VLSI asincrona per un decodificatore Viterbi è progettata utilizzando modelli Quasi Delay Insensitive (QDI) e Differential Cascode Voltage Switch Logic (DCVSL). Viene fornita una panoramica dell'implementazione asincrona. 56 pp. Italienisch.
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Language: Portuguese
Published by Edições Nosso Conhecimento Mrz 2023, 2023
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Este livro discute a concepção da lógica assíncrona e a sua importância na concepção digital. A maioria dos descodificadores concebidos e fabricados actualmente são síncronos. O problema da inclinação do relógio é um grande desafio…na concepção síncrona. Alternativamente, os sistemas assíncronos estão a tornar-se familiares, pois não necessitam de relógio global, uma vez que estes sistemas são sincronizados localmente por meio de protocolos de comunicação. A arquitectura VLSI assíncrona para um descodificador Viterbi é concebida utilizando modelos Quasi Delay Insensitive (QDI) e Differential Cascode Voltage Switch Logic (DCVSL). Oferece uma visão geral da implementação assíncrona. 56 pp. Portugiesisch.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Dieses Buch behandelt den Entwurf asynchroner Logik und ihre Bedeutung für den digitalen Entwurf. Die meisten der heute entwickelten und hergestellten Decoder sind synchron. Das Problem des Taktversatzes ist eine große Herausforderu…ng beim synchronen Entwurf. Alternativ dazu werden asynchrone Systeme immer vertrauter, da sie keinen globalen Taktgeber benötigen, da diese Systeme durch Kommunikationsprotokolle lokal synchronisiert werden. Die asynchrone VLSI-Architektur für einen Viterbi-Decoder wird unter Verwendung von Quasi Delay Insensitive (QDI) Templates und Differential Cascode Voltage Switch Logic (DCVSL) entworfen. Sie gibt einen Überblick über die asynchrone Implementierung. 56 pp. Deutsch.
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Ce livre traite de la conception de la logique asynchrone et de son importance dans la conception numérique. La plupart des décodeurs conçus et fabriqués aujourd'hui sont synchrones. Le problème du décalage d'horloge est un défi majeur…dans la conception synchrone. Par ailleurs, les systèmes asynchrones deviennent de plus en plus familiers, car ils n'ont pas besoin d'horloge globale et sont synchronisés localement au moyen de protocoles de communication. L'architecture VLSI asynchrone d'un décodeur de Viterbi est conçue à l'aide de modèles quasi insensibles au délai (QDI) et d'une logique de commutation de tension en cascade différentielle (DCVSL). Il donne un aperçu de la mise en ¿uvre asynchrone.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Französisch.
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Ce livre traite de la conception de la logique asynchrone et de son importance dans la conception numérique. La plupart des décodeurs conçus et fabriqués aujourd'hui sont synchrones. Le problème du décalage d'horloge est un défi majeur d…ans la conception synchrone. Par ailleurs, les systèmes asynchrones deviennent de plus en plus familiers, car ils n'ont pas besoin d'horloge globale et sont synchronisés localement au moyen de protocoles de communication. L'architecture VLSI asynchrone d'un décodeur de Viterbi est conçue à l'aide de modèles quasi insensibles au délai (QDI) et d'une logique de commutation de tension en cascade différentielle (DCVSL). Il donne un aperçu de la mise en oeuvre asynchrone.
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviLa dott.ssa T. Kalavathi Devi ha conseguito la laurea e il dottorato di ricerca presso la GCT di Coimbatore. Le sue aree di interesse comprendono la progettazione VLSI, i circ…uiti a bassa potenza e la proge.
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviDr. T. Kalavathi Devi absolvierte ihr UG und PG in GCT, Coimbatore. Zu ihren Interessensgebieten gehoeren VLSI-Design, Low-Power-Schaltungen und elektronisches Systemdesign. S…ie hat in renommierten Fachzeits.
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Dieses Buch behandelt den Entwurf asynchroner Logik und ihre Bedeutung für den digitalen Entwurf. Die meisten der heute entwickelten und hergestellten Decoder sind synchron. Das Problem des Taktversatzes ist eine große Herausforderung b…eim synchronen Entwurf. Alternativ dazu werden asynchrone Systeme immer vertrauter, da sie keinen globalen Taktgeber benötigen, da diese Systeme durch Kommunikationsprotokolle lokal synchronisiert werden. Die asynchrone VLSI-Architektur für einen Viterbi-Decoder wird unter Verwendung von Quasi Delay Insensitive (QDI) Templates und Differential Cascode Voltage Switch Logic (DCVSL) entworfen. Sie gibt einen Überblick über die asynchrone Implementierung.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Deutsch.
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Language: Portuguese
Published by Edições Nosso Conhecimento Mär 2023, 2023
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Este livro discute a concepção da lógica assíncrona e a sua importância na concepção digital. A maioria dos descodificadores concebidos e fabricados actualmente são síncronos. O problema da inclinação do relógio é um grande desafio na c…oncepção síncrona. Alternativamente, os sistemas assíncronos estão a tornar-se familiares, pois não necessitam de relógio global, uma vez que estes sistemas são sincronizados localmente por meio de protocolos de comunicação. A arquitectura VLSI assíncrona para um descodificador Viterbi é concebida utilizando modelos Quasi Delay Insensitive (QDI) e Differential Cascode Voltage Switch Logic (DCVSL). Oferece uma visão geral da implementação assíncrona.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Portugiesisch.
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Questo libro tratta la progettazione della logica asincrona e la sua importanza nella progettazione digitale. La maggior parte dei decodificatori progettati e realizzati oggi sono sincroni. Il problema del clock skew è una sfida importa…nte nella progettazione sincrona. In alternativa, i sistemi asincroni stanno diventando familiari perché non hanno bisogno di un orologio globale, in quanto sono sincronizzati localmente per mezzo di protocolli di comunicazione. L'architettura VLSI asincrona per un decodificatore Viterbi è progettata utilizzando modelli Quasi Delay Insensitive (QDI) e Differential Cascode Voltage Switch Logic (DCVSL). Viene fornita una panoramica dell'implementazione asincrona.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Italienisch.
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Dieses Buch behandelt den Entwurf asynchroner Logik und ihre Bedeutung für den digitalen Entwurf. Die meisten der heute entwickelten und hergestellten Decoder sind synchron. Das Problem des Taktversatzes ist eine große Herausforderung be…im synchronen Entwurf. Alternativ dazu werden asynchrone Systeme immer vertrauter, da sie keinen globalen Taktgeber benötigen, da diese Systeme durch Kommunikationsprotokolle lokal synchronisiert werden. Die asynchrone VLSI-Architektur für einen Viterbi-Decoder wird unter Verwendung von Quasi Delay Insensitive (QDI) Templates und Differential Cascode Voltage Switch Logic (DCVSL) entworfen. Sie gibt einen Überblick über die asynchrone Implementierung.
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Questo libro tratta la progettazione della logica asincrona e la sua importanza nella progettazione digitale. La maggior parte dei decodificatori progettati e realizzati oggi sono sincroni. Il problema del clock skew è una sfida importan…te nella progettazione sincrona. In alternativa, i sistemi asincroni stanno diventando familiari perché non hanno bisogno di un orologio globale, in quanto sono sincronizzati localmente per mezzo di protocolli di comunicazione. L'architettura VLSI asincrona per un decodificatore Viterbi è progettata utilizzando modelli Quasi Delay Insensitive (QDI) e Differential Cascode Voltage Switch Logic (DCVSL). Viene fornita una panoramica dell'implementazione asincrona.
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Este livro discute a concepção da lógica assíncrona e a sua importância na concepção digital. A maioria dos descodificadores concebidos e fabricados actualmente são síncronos. O problema da inclinação do relógio é um grande desafio na co…ncepção síncrona. Alternativamente, os sistemas assíncronos estão a tornar-se familiares, pois não necessitam de relógio global, uma vez que estes sistemas são sincronizados localmente por meio de protocolos de comunicação. A arquitectura VLSI assíncrona para um descodificador Viterbi é concebida utilizando modelos Quasi Delay Insensitive (QDI) e Differential Cascode Voltage Switch Logic (DCVSL). Oferece uma visão geral da implementação assíncrona.
