Rama Murthy L (3 results)

Systolic Array Based Discrete Wavelet Transform: First Edition
Hemanth, J.; Chandra Sekhar, C.; Rama Murthy, L.; Hemanth, J.; Chandra Sekhar, C.; Rama Murthy, L.
- Softcover
Seller: Revaluation Books, Exeter, United KingdomRevaluation Books
Contact seller5-star sellerCondition: New
£ 85.03
£ 10.00 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Paperback. Condition: Brand New. 108 pages. 8.66x5.91x0.25 inches. In Stock.

- Softcover
- Print on Demand
Seller: moluna, Greven, Germanymoluna
Contact seller5-star sellerCondition: New
£ 36.79
£ 42.00 shippingShips from Germany to U.S.A.Quantity: Over 20 available
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Hemanth J.Mr. J.Hemanth is working as an Asst. Professor in Dept. of ECE, Vemu IT,P.Kothakota, Chittoor (D), A.P, India, pursued his M.Tech from SVCET, affiliated to JNTUA, Chittoor (D)in the year 2012 and B.Tech from KEC,Kuppam, aff. …

Language: English
Published by LAP LAMBERT Academic Publishing Okt 2012, 2012
- Softcover
- Print on Demand
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germanybuchversandmimpf2000
Contact seller5-star sellerCondition: New
£ 173.07
£ 51.44 shippingShips from Germany to U.S.A.Quantity: 1 available
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Now a days due to limitations in communication bandwidth there is more demand for compression in applications like multimedia communication, Television, Video Conferencing etc. This can be done by using DWT(Discrete Wavelet Transform) or DCT (Discrete Cosine Transform). DCT has poor reconstructed image when high compression is performed hence DWT is used. This book presents an implementation of DWT using Systolic architecture in VLSI .This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power. The architecture is simple, modular, and cascadable for computation of one, or multi-dimensional DWT. Finally comparison of results of Systolic Array architecture and the lifting based architecture is done, which showed that prior is much faster.OmniScriptum SRL, Str. Armeneasca 28/1, office 1, 2012 Chisinau 108 pp. Englisch.…