Nandyala Naveena (9 results)

Condition: New.

Condition: New.

paperback. Condition: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology. 60 pp. Englisch. …

Condition: New. Print on Demand.

Condition: New. PRINT ON DEMAND.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology.…

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 60 pp. Englisch.…

Taschenbuch. Condition: Neu. GDI: Power & Area Efficient Digital Circuits for Portable Devices | Nandyala Naveena (u. a.) | Taschenbuch | Englisch | 2020 | LAP LAMBERT Academic Publishing | EAN 9786202685146 | Verantwortliche Person für die EU: LAP Lambert Academic Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu Print on Demand. …