Gawish Eman (6 results)

Taschenbuch. Condition: Neu. Variability Tolerant Networks on Chip | Eman Gawish | Taschenbuch | 132 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659660900 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for different technology nodes and NoC size. Finally, variability-aware routing algorithms make use of process variability link failure probability and adapt routing to reduce the NoC failure rate. 132 pp. Englisch.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Gawish EmanEman Kamel Gawish received the Ph.D. in Electronics and Electrical Communications Engineering from Cairo University, Giza, Egypt, in 2013. Her general research interests are in advanced system architectures, especially net.

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for different technology nodes and NoC size. Finally, variability-aware routing algorithms make use of process variability link failure probability and adapt routing to reduce the NoC failure rate.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 132 pp. Englisch.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for different technology nodes and NoC size. Finally, variability-aware routing algorithms make use of process variability link failure probability and adapt routing to reduce the NoC failure rate.