David V Overhauser (33 results)
- Hardcover
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Hardcover. Condition: Good. No Jacket. Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less.
Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science, 66)
Rao, Vasant B.; Overhauser, David V.; Trick, Timothy N.; Hajj, Ibrahim N.
- Softcover
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Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science, 66)
Rao, Vasant B.; Overhauser, David V.; Trick, Timothy N.; Hajj, Ibrahim N.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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- Hardcover
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Condition: Gut. Zustand: Gut | Seiten: 292 | Sprache: Englisch | Produktart: Bücher | Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-tim…ing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
Switch-level Timing Simulation of Mos Vlsi Circuits
Rao, Vasant B.; Overhauser, David V.; Trick, Timothy N.; Hajj, Ibrahim N.
- Softcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
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- Hardcover
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Condition: New. pp. 224.
- Softcover
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Condition: New. pp. 224.
Switch-Level Timing Simulation of MOS VLSI Circuits
Vasant B. Rao|David V. Overhauser|Timothy N. Trick|Ibrahim N. Hajj
- Hardcover
Seller: moluna, Greven, , Germanymoluna
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£ 105.68
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Condition: New. Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In thos.
- Softcover
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- Hardcover
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Switch-Level Timing Simulation of MOS VLSI Circuits
Vasant B. Rao|David V. Overhauser|Timothy N. Trick|Ibrahim N. Hajj
- Softcover
Seller: moluna, Greven, , Germanymoluna
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£ 113.65
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Condition: New. Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In thos.
- Softcover
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- Softcover
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Condition: New. pp. 294 Index.
Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science (66))
Rao, Vasant B., Overhauser, David V., Trick, Timothy N., Haj
- Softcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
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Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science, 66)
Rao, Vasant B., Overhauser, David V., Trick, Timothy N., Haj
- Hardcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
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£ 155.00
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- Hardcover
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£ 183.12
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Condition: New. pp. 292 Index.
Switch-level Timing Simulation of Mos Vlsi Circuits
Rao, Vasant B.; Overhauser, David V.; Trick, Timothy N.; Hajj, Ibrahim N.
- Softcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
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£ 188.02
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Condition: As New. Unread book in perfect condition.
- Softcover
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing,… switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
- Softcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
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- Softcover
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- Hardcover
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Hardcover. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Hardcover
- Print on Demand
Seller: Majestic Books, Hounslow, , United KingdomMajestic Books
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£ 127.22
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Condition: New. Print on Demand pp. 224 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
- Softcover
- Print on Demand
Seller: Majestic Books, Hounslow, , United KingdomMajestic Books
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£ 128.73
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Condition: New. Print on Demand pp. 224 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
- Softcover
- Print on Demand
Seller: Biblios, frankfurt am main, HESSE, GermanyBiblios
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Condition: New. PRINT ON DEMAND pp. 224.
- Hardcover
- Print on Demand
Seller: Biblios, frankfurt am main, HESSE, GermanyBiblios
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Condition: New. PRINT ON DEMAND pp. 224.
- Softcover
- Print on Demand
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, , GermanyBuchWeltWeit Ludwig Meier e.K.
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£ 142.95
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timi…ng, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. 292 pp. Englisch.
- Softcover
- Print on Demand
Seller: moluna, Greven, , Germanymoluna
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented i…n circuit, timing, fast-timi.
- Hardcover
- Print on Demand
Seller: moluna, Greven, , Germanymoluna
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Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques imp…lemented in circuit, timing, fast-timi.
- Softcover
- Print on Demand
Seller: Majestic Books, Hounslow, , United KingdomMajestic Books
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£ 191.21
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Condition: New. Print on Demand pp. 294 Figures, 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
- Hardcover
- Print on Demand
Seller: Majestic Books, Hounslow, , United KingdomMajestic Books
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£ 191.72
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Condition: New. Print on Demand pp. 292 Figures, 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
