Ciprian Seiculescu (3 results)
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Seller: preigu, Osnabrück, Germanypreigu
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Taschenbuch. Condition: Neu. Design Framework and Methodology for Synthesis of Networks-On-Chip | Synthesis of Networks-On-Chip on FPGA Platforms and 3D Integrated Chips | Ciprian Seiculescu | Taschenbuch | Englisch | VDM Verlag Dr. Müller | EAN 9783639241655 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher… Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Seller: moluna, Greven, Germanymoluna
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Kartoniert / Broschiert. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Seiculescu CiprianCiprian Seiculescu received his B.S. in automation and applied informatics in 2006 from University Politehnica of Timisoara (Romania). He received his M.S. in…computer science in 2008 from the Swiss Federal Instit.
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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - With the increasing demands of today and tomorrow s applications, chips become communication dominated. Traditional bus-based architectures are struggling because they cannot scale to application demands. New architectural paradigms were… developed to cope with communication demands, called Networks-on-Chips (NoC). NoC are micro networks that are inspired from general networks and which solve the scalability problem. Designers still have to cope with the complexity of systems and in order to meet the time-to-market constraint they need good design flows and tools to automate the design process of complex Multi Processor Systems-on-Chip (MPSoC). A method is presented to automate prototyping of NoCs on FPGAs. FPGA emulation was added to the back-end of the design flow as an alternative to full system simulation. The program designed to automate the generation of emulation platforms is discussed. Extensions to the front-end tool of the design flow that generates topologies from communication specifications are also presented. The tool was extended to generate topologies for 3D chips. The constraints necessary for this task and the results are discussed.
