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Wafer Level Testing Test During by Sudarshan Bahukudumbi (2 results)
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)
Published by Artech House Publishers, 2010
ISBN 10: 1596939893 ISBN 13: 9781596939899
Language: English
£ 45.92
Convert currency£ 22.29 shipping from U.S.A. to United KingdomQuantity: 1 available
Add to basketHardcover. Condition: New. SHRINK-WRAPPED NEW: US SELLER SHIPS FAST FROM USA.
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Hardcover. Condition: Like New. Like New. book.
