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Phase Locked Loop Circuit Design (9 results)
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paperback. Condition: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority!
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Hardcover. Condition: Very Good. No Jacket. 1st Edition. Light foxing to top edge of text block. Name stamp on fore edge and inside front cover.
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Phase-Locked Loop Circuit Design
First Edition
Soft cover. Condition: Very Good. 1st Edition. A crisp, unmarked softcover in very good condition; light crease to top corner on rear of cover, faint sunning to spine. We are a brick-and-mortar store and sell our own inventory.
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Phase-Locked Loop Circuit Design
Language: English
Published by Prentice Hall, Englewood Cliffs, 1991
ISBN 10: 0136627439 ISBN 13: 9780136627432
Seller: Argosy Book Store, ABAA, ILAB, New York, NY, U.S.A.
Seller rating 5 out of 5 stars
Signed
hardcover. Condition: very good. Many tables and graphs. x + 262 pages, 8vo, printed cloth; edges foxed and with small dent in front gutter. Englewood Cliffs: Prentice Hall, (1991). A very good copy. Presentation copy signed by the author.
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Condition: new.
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Condition: Fair. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In fair condition, suitable as a study copy. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,600grams, ISBN:9780136627432.
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Design and Modeling of PLL Based CDR for Inter Chip Communications | Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated Circuit for 10 Gb/s Intra/Inter Chip Communications in SoC
Language: English
Published by VDM Verlag Dr. Müller, 2009
ISBN 10: 3639185544 ISBN 13: 9783639185546
Taschenbuch. Condition: Neu. Design and Modeling of PLL Based CDR for Inter Chip Communications | Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated Circuit for 10 Gb/s Intra/Inter Chip Communications in SoC | Maher Assaad | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2009 | VDM Verlag Dr. Müller | EAN 9783639185546 | Verantwortliche Person für die EU: OmniScriptum GmbH & Co. KG, Bahnhofstr. 28, 66111 Saarbrücken, info[at]akademikerverlag[dot]de | Anbieter: preigu.
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phase-locked loop (PLL) circuit design and application(Chinese Edition)
Language: Chinese
Published by Science Press Pub. Date :2006-01-01, 1991
ISBN 10: 7030165284 ISBN 13: 9787030165282
Soft cover. Condition: New. Language:Chinese.Author:(RI)YUAN BAN JUN ZHAO HE XI CAI YI.Binding:Soft cover.Publisher:Science Press Pub. Date :2006-01-01.
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Design and Modeling of PLL Based CDR for Inter Chip Communications : Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated Circuit for 10 Gb/s Intra/Inter Chip Communications in SoC
Language: English
Published by VDM Verlag Dr. Müller, 2009
ISBN 10: 3639185544 ISBN 13: 9783639185546
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This work describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modeled at gate level using the Verilog-A language and time-domain simulated.
