Design and Modeling of PLL Based CDR for Inter Chip Communications | Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated Circuit for 10 Gb/s Intra/Inter Chip Communications in SoC

Maher Assaad

ISBN 10: 3639185544 ISBN 13: 9783639185546
Published by VDM Verlag Dr. Müller, 2009
Language: English
Condition: New Soft cover

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New - Soft cover

Condition: New

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