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Hierarchical Modeling Vlsi Circuit by Bhattacharya Debashis (27 results)
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Hardcover. Condition: New. US SELLER SHIPS FAST FROM USA.
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Condition: New. SUPER FAST SHIPPING.
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Condition: New. SUPER FAST SHIPPING.
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Condition: New.
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Hierarchical Modeling for Vlsi Circuit Testing
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Seller rating 5 out of 5 stars
Condition: New.
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Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. In.
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Condition: As New. Unread book in perfect condition.
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Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. In.
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Condition: New. pp. 176.
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Condition: New. pp. 176.
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Hierarchical Modeling for Vlsi Circuit Testing
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Seller rating 5 out of 5 stars
Condition: As New. Unread book in perfect condition.
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Hierarchical Modeling for VLSI Circuit Testing
Published by Kluwer Academic Publishers, 1989
ISBN 10: 079239058X ISBN 13: 9780792390589
Language: English
Seller: Kennys Bookshop and Art Galleries Ltd., Galway, GY, Ireland
Seller rating 5 out of 5 stars
Condition: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 160 pages, biography. BIC Classification: T; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 11. Weight in Grams: 940. . 1989. Hardback. . . . .
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Gebunden. Condition: New. Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated .
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Taschenbuch. Condition: Neu. Hierarchical Modeling for VLSI Circuit Testing | Debashis Bhattacharya (u. a.) | Taschenbuch | xii | Englisch | 2011 | Springer | EAN 9781461288190 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Hierarchical Modeling for VLSI Circuit Testing
Published by Kluwer Academic Publishers, 1989
ISBN 10: 079239058X ISBN 13: 9780792390589
Language: English
Condition: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 160 pages, biography. BIC Classification: T; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 11. Weight in Grams: 940. . 1989. Hardback. . . . . Books ship from the US and Ireland.
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Paperback. Condition: Like New. Like New. book.
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Hierarchical Modeling for VLSI Circuit Testing
Published by Springer Us Dez 1989, 1989
ISBN 10: 079239058X ISBN 13: 9780792390589
Language: English
Buch. Condition: Neu. Neuware - Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
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Hierarchical Modeling for VLSI Circuit Testing
Seller: Celler Versandantiquariat, Eicklingen, Germany
Association Member: GIAQ
Seller rating 5 out of 5 stars
Kluwer, Boston, 1990. X, 159 pages with some graphics, hard cover----former library book in good condition- 460 Gramm.
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Hierarchical Modeling for VLSI Circuit Testing
Published by Springer, Springer Sep 2011, 2011
ISBN 10: 1461288193 ISBN 13: 9781461288190
Language: English
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. 176 pp. Englisch.
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated .
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Condition: New. Print on Demand pp. 176 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
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Condition: New. Print on Demand pp. 176 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
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Hierarchical Modeling for VLSI Circuit Testing
Seller: THE SAINT BOOKSTORE, Southport, United Kingdom
Seller rating 5 out of 5 stars
Hardback. Condition: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 970.
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Condition: New. PRINT ON DEMAND pp. 176.
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Condition: New. PRINT ON DEMAND pp. 176.
