Advanced Mtcmos Based Adder Architectures by Ranjan Mrinal (5 results)

PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Paperback. Condition: new. Paperback. This book presents the design and performance analysis of low-power adder architectures for deep-submicron CMOS VLSI systems. It focuses on transistor-level implementation of Ripple Carry Adder (RCA) and variable-block Carry Select Adder (CSLA) architectures in 90 nm CMOS using Cadence Virtuoso and Spectre. The book examines 4-bit, 8-bit, 16-bit, and 32-bit configurations, with particular emphasis on the trade-offs among propagation delay, dynamic power, leakage power, Power-Delay Product (PDP), and hardware complexity. MTCMOS-based power gating using PMOS header sleep transistors is integrated to suppress standby leakage, while sleep-transistor sizing is investigated to balance leakage reduction against delay overhead. The comparative results demonstrate that RCA offers lower hardware complexity and power consumption, whereas CSLA provides superior speed. The work provides practical insights into designing energy-efficient arithmetic circuits for low-power VLSI applications. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.…

Taschenbuch. Condition: Neu. Advanced MTCMOS-Based Adder Architectures: RCA and Variable-Block CSLA | Mrinal Ranjan (u. a.) | Taschenbuch | Englisch | 2026 | LAP LAMBERT Academic Publishing | EAN 9786630481839 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.…

Paperback. Condition: new. Paperback. This book presents the design and performance analysis of low-power adder architectures for deep-submicron CMOS VLSI systems. It focuses on transistor-level implementation of Ripple Carry Adder (RCA) and variable-block Carry Select Adder (CSLA) architectures in 90 nm CMOS using Cadence Virtuoso and Spectre. The book examines 4-bit, 8-bit, 16-bit, and 32-bit configurations, with particular emphasis on the trade-offs among propagation delay, dynamic power, leakage power, Power-Delay Product (PDP), and hardware complexity. MTCMOS-based power gating using PMOS header sleep transistors is integrated to suppress standby leakage, while sleep-transistor sizing is investigated to balance leakage reduction against delay overhead. The comparative results demonstrate that RCA offers lower hardware complexity and power consumption, whereas CSLA provides superior speed. The work provides practical insights into designing energy-efficient arithmetic circuits for low-power VLSI applications. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.…