9783659693021 - Delay Aware Topology Generation for Network on Chip by Lit, Asrani; Mahyan, Fariza; Mahyan, Termimi Hidayat (6 results)

Taschenbuch. Condition: Neu. Delay Aware Topology Generation for Network on Chip | Asrani Lit (u. a.) | Taschenbuch | 72 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659693021 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topology of NoC. Analysis performances of VOPD is based on the value of hops involved, since VOPD is divided into bisection and quadsection form. Overall, the report proved that the decreased number of hops of VOPD will give a low rate of delay in NoC performances. 72 pp. Englisch.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Lit AsraniAsrani Lit is with Department of Electrical & Electronic, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS). He obtained his master degree of engineering in Electrical (Microelectronics & Computer System) in 2011.

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topology of NoC. Analysis performances of VOPD is based on the value of hops involved, since VOPD is divided into bisection and quadsection form. Overall, the report proved that the decreased number of hops of VOPD will give a low rate of delay in NoC performances.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 72 pp. Englisch.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topology of NoC. Analysis performances of VOPD is based on the value of hops involved, since VOPD is divided into bisection and quadsection form. Overall, the report proved that the decreased number of hops of VOPD will give a low rate of delay in NoC performances.