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Suthar Haresh (7 results)
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Reduction of Test Time During Design for Testability
Language: English
Published by LAP LAMBERT Academic Publishing, 2021
ISBN 10: 6204731947 ISBN 13: 9786204731940
Condition: New.
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Reducción del tiempo de prueba durante el diseño para la comprobabilidad
Language: Spanish
Published by Ediciones Nuestro Conocimiento, 2022
ISBN 10: 6204420208 ISBN 13: 9786204420202
Kartoniert / Broschiert. Condition: New.
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Réduction du temps de test pendant la conception pour la testabilité
Language: French
Published by Editions Notre Savoir, 2022
ISBN 10: 6204420224 ISBN 13: 9786204420226
Kartoniert / Broschiert. Condition: New.
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Redução do tempo de teste durante a concepção para a Testabilidade
Language: Portuguese
Published by Edições Nosso Conhecimento, 2022
ISBN 10: 6204420151 ISBN 13: 9786204420158
Condition: New.
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Kartoniert / Broschiert. Condition: New.
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Kartoniert / Broschiert. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Da die VLSI-Technologie staendig auf kleinere Technologieknoten schrumpft, benoetigen wir eine effiziente Testtechnik. Zuverlaessigkeit und Testbarkeit sind die wichtigsten Parameter beim heutigen VLSI-Design. Die Verkuerzung der Testzeit ist eine grosse Herausf.
