Katevenis (16 results)

Hardcover. Condition: Good. No Jacket. Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less.

Hardcover. Condition: Good. No Jacket. First. 215pp, Wear, soil. Weight is 2.5 lb. W/full markings and pocket. Slight bow. Ex-Library Size: 8vo. Book.

Hardcover. Condition: Very Good. No Jacket. First. 215pp, Wear, soil. Weight is 2.5 lb. W/full markings and pocket. Ex-Library Size: 8vo. Book.

Wrappers. Condition: Good Plus. 1st Edition. 107 pages. A State Attorney from Greece visits New York City, Washington D.C., Virginia, Chicago, Colorado, Utah, and California in 1951. Covers are lightly soiled; small closed tear at top of spine; previous owner's gift inscription. Good plus, wrappers. (119).

Condition: New. In.

PF. Condition: New.

Condition: New. pp. 418.

Paperback. Condition: Brand New. spiral-bound edition. 397 pages. 9.00x6.00x0.75 inches. In Stock.

Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field.

Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condition: Gut. Zustand: Gut | Seiten: 416 | Sprache: Englisch | Produktart: Bücher | This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field.

Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field. 416 pp. Englisch.

Condition: New. Print on Demand pp. 418 Illus.

Condition: New. PRINT ON DEMAND pp. 418.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Goeteborg, Sweden, January 27-29, 2008. The 25 revised.

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Invited Program.- Supercomputing for the Future, Supercomputing from the Past (Keynote).- I Multithreaded and Multicore Processors.- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing.- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect.- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE.- IIa Reconfigurable - ASIP.- BRAM-LUT Tradeoff on a Polymorphic DES Design.- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.- IIb Compiler Optimizations.- Fast Bounds Checking Using Debug Register.- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.- III Industrial Processors and Application Parallelization.- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.- Experiences with Parallelizing a Bio-informatics Program on the Cell BE.- Drug Design Issues on the Cell BE.- IV Power-Aware Techniques.- Coffee: COmpiler Framework for Energy-Aware Exploration.- Integrated CPU Cache Power Management in Multiple Clock Domain Processors.- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.- V High-Performance Processors.- The Significance of Affectors and Affectees Correlations for Branch Prediction.- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator.- LPA: A First Approach to the Loop Processor Architecture.- VI Profiles: Collection and Analysis.- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm.- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy.- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior.- VII Optimizing Memory Performance.- MLP-Aware Dynamic Cache Partitioning.- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory.- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 416 pp. Englisch.