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System on Chip: Next Generation Electronics (Volume 18)
Published by Institution Of Engineering And Technology, 2006
ISBN 10: 0863415520 ISBN 13: 9780863415524
Language: English
Condition: Good. Volume 18. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,1550grams, ISBN:9780863415524.
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System-on-Chip: Next Generation Electronics (Volume 18)
Published by Institution Of Engineering And Technology, 2006
ISBN 10: 0863415520 ISBN 13: 9780863415524
Language: English
Condition: Fair. Volume 18. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In fair condition, suitable as a study copy. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,1550grams, ISBN:9780863415524.
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System on Chip: Next Generation Electronics (Volume 18)
Published by Institution Of Engineering And Technology, 2006
ISBN 10: 0863415520 ISBN 13: 9780863415524
Language: English
Condition: Good. Volume 18. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,1550grams, ISBN:9780863415524.
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System-on-Chip: Next Generation Electronics (Circuits, Devices and Systems) (Circuits, Devices and Systems)
Published by Institution of Engineering and T, 2006
ISBN 10: 0863415520 ISBN 13: 9780863415524
Language: English
Seller: Books From California, Simi Valley, CA, U.S.A.
Seller rating 5 out of 5 stars
£ 9.28
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Add to basketHardcover. Condition: Fine. Sealed in original plastic with major tearing.
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System on Chip: Next Generation Electronics
Published by Institution Of Engineering And Technology, 2006
ISBN 10: 0863415520 ISBN 13: 9780863415524
Language: English
Condition: Good. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. Clean from markings With owner's name inside cover. In good all round condition. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,1550grams, ISBN:9780863415524.
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£ 30.06
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Add to basketCondition: Very Good. Former library book; may include library markings. Used book that is in excellent condition. May show signs of wear or have minor defects.
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£ 30.07
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Add to basketHardcover. Condition: Very Good. No Jacket. May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 1.3.
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Power-Constrained Testing of VLSI Circuits (Frontiers in Electronic Testing)
Seller: Zubal-Books, Since 1961, Cleveland, OH, U.S.A.
Seller rating 5 out of 5 stars
£ 29.84
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Add to basketCondition: Good. 178 pp., Hardcover, ex library else text clean and binding tight. - If you are reading this, this item is actually (physically) in our stock and ready for shipment once ordered. We are not bookjackers. Buyer is responsible for any additional duties, taxes, or fees required by recipient's country.
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£ 29.02
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Add to basketCondition: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher.
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£ 24.40
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Add to basketHardcover. Condition: Used: Good. 2003 hardcover no dj as issued xlibrary copy withdrawn stamp on edge of pages/ in book clean text 178 pages::: J-10.
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System on Chip : Next Generation Electronics
Published by The Institution of Electrical Engineers, London, 2006
Seller: PsychoBabel & Skoob Books, Didcot, United Kingdom
Seller rating 5 out of 5 stars
hardcover. Condition: Very Good. Dust Jacket Condition: No Dust Jacket. Hard cover with no jacket. Book is in very good condition. Very light wear in a few places at edges and corners. Previous owner's name to FEP. Thin mark vertically down inside of cover. Contents are otherwise clean, bright and tight. J. Used.
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£ 80.94
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£ 95.50
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Power-constrained Testing of Vlsi Circuits
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System-Level Design Techniques for Energy-Efficient Embedded Systems
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing, 22B)
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System-Level Design Techniques for Energy-Efficient Embedded Systems
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System-Level Design Techniques for Energy-Efficient Embedded Systems
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Power-constrained Testing of Vlsi Circuits
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Add to basketTaschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.
