System-on-Chip Test Architectures: Nanometer Design for Testability (Volume .)

Language: English

Published by Morgan Kaufmann, 2007

012373973X / 9780123739735

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A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students. Series: Systems on Silicon. Num Pages: 896 pages, Approx. 600 illustrations. BIC Classification: THR. Category: (P) Professional & Vocational. Dimension: 242 x 199 x 38. Weight in Grams: 1602. . 2007. 1st Edition. hardcover. . . . . Books ship from the US and Ireland.

Seller Inventory # V9780123739735

Title
System-on-Chip Test Architectures: Nanometer Design for Testability (Volume .)
Author
Wang, Laung-Terng
Publisher
Morgan Kaufmann
Publication year
2007
Condition
New
Binding
Hardcover
Language
English
ISBN 10
012373973X
ISBN 13
9780123739735

Kennys Bookstore

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