Hardware Accelerated Functional Verification

Language: English

Published by LAP LAMBERT Academic Publishing Dez 2011, 2011

384655913X / 9783846559130

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This item is printed on demand - Print on Demand Titel. Neuware -Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified system. The maximum acceleration achieved on the set of experiments was over 130 times.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 60 pp. Englisch.…

Seller Inventory # 9783846559130

Title
Hardware Accelerated Functional Verification
Author
Marcela ¿Imková
Publisher
LAP LAMBERT Academic Publishing Dez 2011
Publication year
2011
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
384655913X
ISBN 13
9783846559130
Item weight
107 grams
Dimensions
220x150x4 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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