Hardware Accelerated Functional Verification: Framework for FPGA-Accelerated Functional Verification - Softcover

Šimková, Marcela

Softcover

ISBN 10: 384655913X ISBN 13: 9783846559130

Publisher: LAP LAMBERT Academic Publishing, 2011

Synopsis

Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified system. The maximum acceleration achieved on the set of experiments was over 130 times.

About this title

About the Author

Ing. Marcela Šimková has obtained her master degree in Computer and Embedded Systems at Brno University of Technology, Faculty of Information Technology in 2011. Since then she continues her studies for a PhD degree at the same university, focusing on functional verification, hardware acceleration and diagnostics.

Edition details

• Publisher: LAP LAMBERT Academic Publishing
• Publication date: 2011
• Language: English
• ISBN 10: 384655913X
• ISBN 13: 9783846559130
• Binding: Paperback
• Number of pages: 60