Fault Tolerant & Testable Sequential Reversible Circuit Design: A Designers Approach to Realize Fault Tolerant Sequential Reversible Circuit

Pareek, Vishal und Sushil Chandra Jain:

ISBN 10: 3659671681 / ISBN 13: 9783659671685

Published by LAP LAMBERT Academic Publishing,, 2015

About this Item

58 Seiten Am unteren Buchschnitt mittels Stempel als "Mängelexemplar" gekennzeichnet, jedoch innen wie außen ein sehr gutes Exemplar, fast wie neu. Die Leseseiten sind tadellos, sauber und ohne Anstreichungen. 9783659671685 Sprache: Englisch Gewicht in Gramm: 127 Taschenbuch, Größe: 15.2 x 0.5 x 22.9 cm. Seller Inventory # 257038

Bibliographic Details

Title: Fault Tolerant & Testable Sequential ...

Publisher: LAP LAMBERT Academic Publishing,

Publication Date: 2015

Binding: Soft cover

About this title

Synopsis:

Fast growing computing demands the power consumption and chip size issues are posing challenges for logic design with conventional technologies because of the above reliability in conventional technologies is also becoming important. Reversible computing is emerging as an alternative that offers high computation speed, high packaging density and low heat dissipation. This book expands on many of the most popular reversible computing topics such as sequential reversible building block, parity preservation and fault tolerant characteristics of sequential circuits for addressing the reliability issues. In this book, we have reported a Pareek gate suitable for low cost flip-flops design and then design methodology to develop flip-flops are incorporated. Finally, these circuits have been converted into fault tolerant circuits by preserving their parity and designs of offline as well as online testable circuits have been proposed. In addition, the text book presents the statistical results of proposed designs over quantum cost as well as other optimization parameters with existing circuits in literature and a significant improvement is achieved in almost all the parameters.