Designing of Low Power, Wide Range ADPLL for Video Applications : All Digital Phase Locked Loop (ADPLL) Design in 65nm CMOS Technology

Language: English

Published by LAP LAMBERT Academic Publishing, 2011

3846554731 / 9783846554739

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nach der Bestellung gedruckt Neuware - Printed after ordering - The objective of this thesis is to design an All Digital Phase Locked Loop (ADPLL) to align the higher frequency signal at the output of the PLL with its input. This work presents a low power All Digital Phase Locked Loop (ADPLL) for the video applications. The ADPLL has wide range of operating input frequency from 10 kHz to 150 kHz. The output range of ADPLL is from 10 MHz to 300 MHz can be used for a variety of applications. The circuit of ADPLL is designed in a CMOS 65 nm technology using a supply voltage of 1 V. This project is designed using Cadence and MATLAB.

Seller Inventory # 9783846554739

Title
Designing of Low Power, Wide Range ADPLL for Video Applications : All Digital Phase Locked Loop (ADPLL) Design in 65nm CMOS Technology
Author
Abdul Raheem Qureshi
Publisher
LAP LAMBERT Academic Publishing
Publication year
2011
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3846554731
ISBN 13
9783846554739
Item weight
161 grams
Dimensions
220x150x7 mm

AHA-BUCH GmbH

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