Designing of Low Power, Wide Range ADPLL for Video Applications: All Digital Phase Locked Loop (ADPLL) Design in 65nm CMOS Technology - Softcover

Qureshi, Abdul Raheem; Qazi, Haris

 
9783846554739: Designing of Low Power, Wide Range ADPLL for Video Applications: All Digital Phase Locked Loop (ADPLL) Design in 65nm CMOS Technology
Softcover
ISBN 10: 3846554731 ISBN 13: 9783846554739
Publisher: LAP LAMBERT Academic Publishing, 2011

Synopsis

The objective of this thesis is to design an All Digital Phase Locked Loop (ADPLL) to align the higher frequency signal at the output of the PLL with its input. This work presents a low power All Digital Phase Locked Loop (ADPLL) for the video applications. The ADPLL has wide range of operating input frequency from 10 kHz to 150 kHz. The output range of ADPLL is from 10 MHz to 300 MHz can be used for a variety of applications. The circuit of ADPLL is designed in a CMOS 65 nm technology using a supply voltage of 1 V. This project is designed using Cadence and MATLAB.

"synopsis" may belong to another edition of this title.

About the Author

Abdul Raheem Qureshi did his M.Sc.from Linkoping University,Sweden in 2010, and Bachelors in Electronic Engineering from NED University (NED UET), Pakistan in 2007. Currently he is working as a Research Assistant at Electronics Design Centre, NED UET. His research interests include RF drivers for wireless communication, RFIC and VLSI design.

"About this title" may belong to another edition of this title.

Publisher
LAP LAMBERT Academic Publishing
Publication date
2011
Language
English
ISBN 10 
3846554731
ISBN 13 
9783846554739
Binding
Paperback
Number of pages
96