Design-for-test and Test Optimization Techniques for Tsv-based 3d Stacked Ics

Noia, Brandon/ Chakrabarty, Krishnendu

ISBN 10: 3319023772 / ISBN 13: 9783319023779

Published by Springer Verlag, 2013

About this Item

2014 edition. 274 pages. 9.50x6.50x0.75 inches. In Stock.

Seller Inventory # x-3319023772

Bibliographic Details

• Title: Design-for-test and Test Optimization Techniques for Tsv-based 3d Stacked Ics
• Publisher: Springer Verlag
• Publication Date: 2013
• Language: English
• ISBN 10: 3319023772
• ISBN 13: 9783319023779
• Binding: Hardcover
• Condition: Brand New
• Weight: 0.64 kilograms

About this title

Synopsis

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

About the Author

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.