Design-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Chakrabarty, Krishnendu; Noia, Brandon

ISBN 10: 3319023772 / ISBN 13: 9783319023779

Published by Springer International Publishing AG, 2013

About this Item

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Num Pages: 263 pages, 18 black & white illustrations, 115 colour illustrations, 23 black & white tables, biogra. BIC Classification: TJFC; TJFD; UYF. Category: (P) Professional & Vocational. Dimension: 243 x 157 x 16. Weight in Grams: 514. . 2013. 2014th Edition. Hardcover. . . . .

Seller Inventory # V9783319023779

Bibliographic Details

• Title: Design-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs
• Publisher: Springer International Publishing AG
• Publication Date: 2013
• Language: English
• ISBN 10: 3319023772
• ISBN 13: 9783319023779
• Binding: Hardcover
• Condition: New

About this title

Synopsis

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

About the Author

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.