Design Space Exploration of Network-on-Chip at System level

Language: English

Published by LAP LAMBERT Academic Publishing Jan 2012, 2012

384732005X / 9783847320050

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This item is printed on demand - Print on Demand Titel. Neuware -About the Book: The goal of this text is to help students, researchers and academicians, who are working in the field of CAD for VLSI. Network-on-Chip(NoC) has been recently developed as an on-chip communication solution for System-on-Chip(SoC) design. This paradigm supports various communication resources at a time and overcomes the limitations of bus-based System. Design space exploration methodology at system level reduces the time-to-market pressure of the large and complex systems. On the other hand, design space exploration at system level is a combinatorial optimization problem. So, multi-objective Genetic Algorithm has been considered as an optimization tool for the design space exploration task. This book provides detailed methodology/algorithms to explore the design space of NoC at System Level using Genetic Algorithm. This book is the outcome of my PhD work. I hope this book will help all stake holders for extensive research in the field of NoC at System level.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 160 pp. Englisch.

Seller Inventory # 9783847320050

Title
Design Space Exploration of Network-on-Chip at System level
Author
Rabindra Kumar Jena
Publisher
LAP LAMBERT Academic Publishing Jan 2012
Publication year
2012
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
384732005X
ISBN 13
9783847320050
Item weight
256 grams
Dimensions
220x150x11 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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