Design of Reconfigurable Decoder for SRAM

Arti Noor

ISBN 10: 3659114162 / ISBN 13: 9783659114168

Published by LAP LAMBERT Academic Publishing Mai 2012, 2012

About this Item

Neuware -Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.Books on Demand GmbH, Überseering 33, 22297 Hamburg 96 pp. Englisch.

Seller Inventory # 9783659114168

Bibliographic Details

• Title: Design of Reconfigurable Decoder for SRAM
• Publisher: LAP LAMBERT Academic Publishing Mai 2012
• Publication Date: 2012
• Language: English
• ISBN 10: 3659114162
• ISBN 13: 9783659114168
• Binding: Taschenbuch
• Condition: Neu

About this title

Synopsis

Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.

About the Author

Dr Arti Noor is woking as Associate Professor at CDAC, NOIDA. She is an alumnus of Banaras Hindi University, Varanasi. Her current interest includes VLSI circuit design and characterization. Mr. Sampath Kumar V is working with JSSATE, Noida and pursuing Ph.D with UPTU, Lucknow. Mr. Abhinav Vishnoi is working with LPU, Jalandhar, Punjab.