Cost-effective Methods for High-speed Nanometer CMOS VLSI Design

Language: English

Published by LAP LAMBERT Academic Publishing Mai 2010, 2010

3838307321 / 9783838307329

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This item is printed on demand - Print on Demand Titel. Neuware -The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 132 pp. Englisch.…

Seller Inventory # 9783838307329

Title
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
Author
Charbel Akl
Publisher
LAP LAMBERT Academic Publishing Mai 2010
Publication year
2010
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3838307321
ISBN 13
9783838307329
Item weight
215 grams
Dimensions
220x150x9 mm

buchversandmimpf2000

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