Comparative Study on Reduction of Sub-Threshold Leakage Current

Language: English

Published by LAP LAMBERT Academic Publishing Jun 2016, 2016

3659899488 / 9783659899485

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -In order to deal with the active power utilization of high-performance digital designs, dynamic leakage control techniques are required to contribute considerable leakage power savings. As technology scales, sub threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. The main objective of this project is to reduce the sub-threshold leakage in a CMOS device by making use of sleep transistors and PMOS logic. A low resistance path is generated by using sleep transistors as keepers to drop down the sub-threshold leakage. This is achieved further by using PMOS logic between the pull-up network (PUN) and pull down network (PDN). A fast and efficient leakage reduction technique is put forward which mitigates the power dissipation in addition to the reduction of leakage current. The main objective of the work is to analyze power and delay at 130nm, 90nm, and 45nm technologies for a CMOS half and full adder as well as subtractor circuits using microwind tool. 100 pp. Englisch.…

Seller Inventory # 9783659899485

Title
Comparative Study on Reduction of Sub-Threshold Leakage Current
Author
Kalagadda Bikshalu
Publisher
LAP LAMBERT Academic Publishing Jun 2016
Publication year
2016
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659899488
ISBN 13
9783659899485
Item weight
167 grams
Dimensions
220x150x6 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany