Items related to FIR Filter Using Adders Based On SPST Technique
Synopsis
Finite impulse response (FIR) filter is basic component used in Digital Signal Processing application. Multiplier is one of the key components used in (FIR) but due to large number of multiplication its hardware gets complex. Design of high speed, low power multipliers is carried out to decrease propagation time and power dissipation of a processing system.Choosing the exact technique and implementing it make a big difference in power dissipation. To enhance speed many changes have been made over the existing booth algorithm. Existing design of Spurious Power Suppression Technique (SPST) based multipliers has been modified to reduce power dissipation and increase speed. Unwanted switching activities can be removed by using this technique. To attain this there are two ways to design a pre-computation unit i.e. by using registers and by using AND gate. Design of SPST based multiplier has been implemented on Xilinx 14.7 using Verilog HDL. Experimental results show that a SPST based multiplier achieved ~45% speed improvement and ~35% of reduction in power dissipation. This proposed multiplier has been used in FIR filter to achieve great extent of reduction in power dissipation.
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About the Author
Jagandeep Kaur is currenlty working as an Assistant Professor in the ECE department, Amity University, Haryana. She received M.Tech. degree from National Institute of Technology, Kurukshetra, Haryana, India. She is pursuing Ph.D. in VLSI design from Amity University, Haryana. Her research interests are analog/mixed signal design.
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FIR Filter Using Adders Based On SPST Technique
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LAP Lambert Academic Publishing Jul 2017, 2017
ISBN 10: 3330331682
ISBN 13: 9783330331686
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Finite impulse response (FIR) filter is basic component used in Digital Signal Processing application. Multiplier is one of the key components used in (FIR) but due to large number of multiplication its hardware gets complex. Design of high speed, low power multipliers is carried out to decrease propagation time and power dissipation of a processing system.Choosing the exact technique and implementing it make a big difference in power dissipation. To enhance speed many changes have been made over the existing booth algorithm. Existing design of Spurious Power Suppression Technique (SPST) based multipliers has been modified to reduce power dissipation and increase speed. Unwanted switching activities can be removed by using this technique. To attain this there are two ways to design a pre-computation unit i.e. by using registers and by using AND gate. Design of SPST based multiplier has been implemented on Xilinx 14.7 using Verilog HDL. Experimental results show that a SPST based multiplier achieved ~45% speed improvement and ~35% of reduction in power dissipation. This proposed multiplier has been used in FIR filter to achieve great extent of reduction in power dissipation. 68 pp. Englisch. Seller Inventory # 9783330331686
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FIR Filter Using Adders Based On SPST Technique
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LAP LAMBERT Academic Publishing, 2017
ISBN 10: 3330331682
ISBN 13: 9783330331686
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Kaur JagandeepJagandeep Kaur is currenlty working as an Assistant Professor in the ECE department, Amity University, Haryana. She received M.Tech. degree from National Institute of Technology, Kurukshetra, Haryana, India. She is purs. Seller Inventory # 155541289
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FIR Filter Using Adders Based On SPST Technique
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ISBN 10: 3330331682
ISBN 13: 9783330331686
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Paperback. Condition: Brand New. 68 pages. 8.66x5.91x0.16 inches. In Stock. Seller Inventory # __3330331682
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FIR Filter Using Adders Based On SPST Technique
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LAP LAMBERT Academic Publishing Jun 2017, 2017
ISBN 10: 3330331682
ISBN 13: 9783330331686
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Finite impulse response (FIR) filter is basic component used in Digital Signal Processing application. Multiplier is one of the key components used in (FIR) but due to large number of multiplication its hardware gets complex. Design of high speed, low power multipliers is carried out to decrease propagation time and power dissipation of a processing system.Choosing the exact technique and implementing it make a big difference in power dissipation. To enhance speed many changes have been made over the existing booth algorithm. Existing design of Spurious Power Suppression Technique (SPST) based multipliers has been modified to reduce power dissipation and increase speed. Unwanted switching activities can be removed by using this technique. To attain this there are two ways to design a pre-computation unit i.e. by using registers and by using AND gate. Design of SPST based multiplier has been implemented on Xilinx 14.7 using Verilog HDL. Experimental results show that a SPST based multiplier achieved ~45% speed improvement and ~35% of reduction in power dissipation. This proposed multiplier has been used in FIR filter to achieve great extent of reduction in power dissipation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch. Seller Inventory # 9783330331686
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FIR Filter Using Adders Based On SPST Technique
Published by
LAP LAMBERT Academic Publishing, 2017
ISBN 10: 3330331682
ISBN 13: 9783330331686
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Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Finite impulse response (FIR) filter is basic component used in Digital Signal Processing application. Multiplier is one of the key components used in (FIR) but due to large number of multiplication its hardware gets complex. Design of high speed, low power multipliers is carried out to decrease propagation time and power dissipation of a processing system.Choosing the exact technique and implementing it make a big difference in power dissipation. To enhance speed many changes have been made over the existing booth algorithm. Existing design of Spurious Power Suppression Technique (SPST) based multipliers has been modified to reduce power dissipation and increase speed. Unwanted switching activities can be removed by using this technique. To attain this there are two ways to design a pre-computation unit i.e. by using registers and by using AND gate. Design of SPST based multiplier has been implemented on Xilinx 14.7 using Verilog HDL. Experimental results show that a SPST based multiplier achieved ~45% speed improvement and ~35% of reduction in power dissipation. This proposed multiplier has been used in FIR filter to achieve great extent of reduction in power dissipation. Seller Inventory # 9783330331686
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FIR Filter Using Adders Based On SPST Technique
Published by
LAP LAMBERT Academic Publishing, 2017
ISBN 10: 3330331682
ISBN 13: 9783330331686
New
Taschenbuch
Seller: preigu, Osnabrück, Germany
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Taschenbuch. Condition: Neu. FIR Filter Using Adders Based On SPST Technique | Jagandeep Kaur (u. a.) | Taschenbuch | 68 S. | Englisch | 2017 | LAP LAMBERT Academic Publishing | EAN 9783330331686 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 109468616