Logic Synthesis Using Synopsys Tm - Hardcover

Kurup, Pran

Hardcover

ISBN 10: 0792395824 ISBN 13: 9780792395829

Publisher: Kluwer Academic Publishers, 1995

Synopsis

Logic synthesis has become a fundamental component of the ASIC design flow. The primary focus of this text is Synopsys Design Compiler TM: one of the leading synthesis tools in the EDA marketplace. The book is specially organized to try and assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 "classic scenarios" faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided.

About this title

From the Back Cover

Logic Synthesis Using Synopsys, Second Edition, is for anyone who hates reading manuals but would still like to learn logic synthesis as practiced in the real world. This book should help the reader develop a better understanding of the logic synthesis design flow, optimization strategies using the Design Compiler, test synthesis using the Test Compiler, commonly used interface formats such as EDIF, SDF and PDEF, Links from the Design Compiler to Layout Tools, the FPGA synthesis process, design re-use in a synthesis-based design methodology and a conceptual introduction to behavioral synthesis. Examples in both VHDL and Verilog have been provided throughout the book. Logic Synthesis Using Synopsys, Second Edition covers several new and emerging areas in addition to improvements in the presentation and contents in chapters from the first edition.

Edition details

• Publisher: Kluwer Academic Publishers
• Publication date: 1995
• Language: English
• ISBN 10: 0792395824
• ISBN 13: 9780792395829
• Binding: Hardcover
• Number of pages: 328