"A Guide to VHDL" is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is a guide for system and chip designers who are working with VHDL CAD tools and who have some experience programming in FORTRAN, PASCAL or C and have used a logic simulator. The work includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapter can be run to reinforce the learning experience. For practical purposes, the book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. The guide can be used as a primer since its contents are appropriate for an introductory course in VHDL.
"synopsis" may belong to another edition of this title.
£ 9 shipping within United Kingdom
Destination, rates & speedsSeller: dsmbooks, Liverpool, United Kingdom
hardcover. Condition: Good. Good. book. Seller Inventory # D8S0-3-M-0792392558-4
Quantity: 1 available
Seller: Buchpark, Trebbin, Germany
Condition: Gut. Zustand: Gut | Seiten: 368 | Sprache: Englisch | Produktart: Bücher. Seller Inventory # 10341999/3
Quantity: 1 available
Seller: HPB-Red, Dallas, TX, U.S.A.
Hardcover. Condition: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! Seller Inventory # S_396462472
Quantity: 1 available