too vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to logical simulation or synthesis. To the very beginner, VHDL appears as a "kit". He is quickly aware that his problem may be solved with VHDL, but does not know how. He does not even know how to start. In this state of mind, all the constraints that can be set to his modeling job, by using a subset of the language or a given design methodology, may be seen as a life preserver. The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: • Why choose VHDL? • Which VHDL tools should be chosen? • Which modeling methodology should be adopted? • How should the VHDL environment be customized? • What are the tricks? Where are the traps? • What are the differences between VHDL and other competing HDLs? Answers to these questions are organized according to different concerns: buying the tools, organizing the environment, and designing. Decisions taken in each of these areas may have many consequences on the way to the acceptance and efficiently use of VHDL in a company.
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VHDL is the most widespread standard for hardware description. From its initial applications in simulation and ASIC description, VHDL is now being used in a wide range of applications at all levels, from system down to gate. The applications, which include synthesis and formal proof, make VHDL a design support tool as well as a deliverable. The use of VHDL implies a new approach to design. The VHDL Designer's Reference offers engineers and students practical help in addressing real problems encountered when implementing and using VHDL in their companies or research laboratories. It is thus a valuable reference for all practising designers. Intended for the experienced designer, VHDL Designer's Reference discusses modeling issues, design methods, efficiency tricks and portability traps. It also compares VHDL with other hardware description languages such as M, Verilog, and UDL/I. This complete reference provides a resource to help improve the designer's use of VHDL.
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Buch. Condition: Neu. VHDL Designer's Reference | Jean-Michel Bergé (u. a.) | Buch | xviii | Englisch | 1992 | Springer US | EAN 9780792317562 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Seller Inventory # 102551014