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Synopsis
This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
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About the Author
Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal
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Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications
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Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications
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Taylor & Francis Ltd, 2020
ISBN 10: 0367573555
ISBN 13: 9780367573553
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Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications
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