ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures

Language: English

Published by LAP LAMBERT Academic Publishing Aug 2018, 2018

6139900611 / 9786139900619

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Multipliers with large bit lengths have a major impact on the performance of digital circuits in many applications like cryptography, digital signal processing and image processing. The performances of many computational problems are often dominated by the speed at which a multiplication operation can be executed. This book gives a brief overview of various multipliers such as Baugh Wooley, Pezaris, Array, Booth, Vedic multipliers and Compressor based multipliers. The main objective is to compare various types of multiplier in terms of power consumption, area and delay. These signed multiplication concepts are implemented in Verilog HDL and implemented in Cadence RTL Compiler with 180nm technology. 52 pp. Englisch.

Seller Inventory # 9786139900619

Title
ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures
Author
Saranya Karunamurthi
Publisher
LAP LAMBERT Academic Publishing Aug 2018
Publication year
2018
Condition
Neu
Signed
Signed by Author(s)
Binding
Taschenbuch
Language
English
ISBN 10
6139900611
ISBN 13
9786139900619
Item weight
96 grams
Dimensions
220x150x4 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany