VHDL Modeling for Digital Design Synthesis

Hsu, Yu-Chin, Kevin F. Tsai, Jessie T. Liu, and Eric S. Lin

ISBN 10: 0792395972 / ISBN 13: 9780792395973

Published by Kluwer Academic Publishers, Boston, 1995

About this Item

A Near Fine copy in original laminated hard covers. Owner's name inside the front cover, else about as new. No dust jacket, apparently as issued.

Seller Inventory # 061418

Bibliographic Details

• Title: VHDL Modeling for Digital Design Synthesis
• Publisher: Kluwer Academic Publishers, Boston
• Publication Date: 1995
• Language: English
• ISBN 10: 0792395972
• ISBN 13: 9780792395973
• Binding: Hardcover
• Edition: First Edition.
• Condition: Near Fine
• Dust Jacket Condition: No Dust Jacket
• Book Type: Book

About this title

Synopsis

The purpose of this book is to introduce VHSIC Hardware Description Lan­ guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per­ mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im­ plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe­ sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under­ graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs.

Synopsis

VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as a hardware description language that permitted the simulation of digital designs, VHDL is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this is that not all of its constructs are useful in synthesis. VHDL has data structures, such as files and pointers, which are useful for simulation but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. VHDL Modeling for Digital Design Synthesis covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum. Audience: Working professionals as well as graduate or undergraduate students who can use the book to get acquainted with VHDL and to learn how it can be used in modeling or digital design.