Principles of Verifiable Rtl Design:; a functional coding style supporting verification processes in Verilog
Language: English
Published by Kluwer Academic Publishers, Norwell, Mass, 2000
- First Edition
- Hardcover
- Used
Seller: BIBLIOPE by Calvello Books, Oakland, CA, U.S.A.BIBLIOPE by Calvello Books
AbeBooks seller since March 19, 1998
Condition: Used
£ 13.71
Quantity: 1 available
Add to basketItem description from seller
Purple octavo; xvii, 253 p, b&w illus; 24 cm. Contents: Register Transfer Level --; What is It? --; Verifiable RTL --; Applying Design Discipline --; The Verification Process --; Specification Design Decomposition --; High-Level Design Requirements --; Block-Level Specification and Design --; RTL Implementation --; Synthesis and Physical Design --; Functional Test Strategies --; Deterministic or Directed Test --; Random Test --; Transaction Analyzer Verification --; Chip Initialization Verification --; Synthesizable Testbench --; Transformation Test Strategies --; Coverage, Events and Assertions --; Coverage --; Ad-hoc Metrics --; Programming Code Metrics --; State Machine and Arc Coverage Metrics --; User Defined Metrics --; Fault Coverage Metrics --; Regression Analysis and Test Suite Optimization --; Event Monitors and Assertion Checkers --; Events --; Assertions --; Assertion Monitor Library Details --; Event Monitor and Assertion Checker Methodology --; Linting Strategy --; Implementation Considerations --; Event Monitor Database and Analysis --; RTL Methodology Basics --; Simple RTL Verifiable Subset --; Linting --; Linting in a design project --; Lint description --; Project Oriented --; Linting Message Examples --; Object-Based Hardware Design --; OBHD and Simulation --; OBHD and Formal Verification --; OBHD and Physical Design --; OBHD Synthesis --; OBHD Scan Chain Hookup --; A Text Macro Implementation --; RTL Logic Simulation --; Simulation History --; First Steps --; X, Z and Other States --; Function and Timing --; Gate to RTL Migration --; Acceleration and Emulation --; Language Standardization. Integrated circuits -- Very large scale integration -- Computer-aided design. Faint rubbed fold to spine head & foot & folds, barely rubbed corners, else near fine(+). First edition (presumed; no earlier dates stated). …
Seller Inventory # 23856
- Title
- Principles of Verifiable Rtl Design:; a functional coding style supporting verification processes in Verilog
- Author
- Bening, Lionel; Foster, Harry
- Publisher
- Kluwer Academic Publishers, Norwell, Mass
- Publication year
- 2000
- Condition
- near fine(+)
- Binding
- Hardcover
- Language
- English
- ISBN 10
- 0792377885
- ISBN 13
- 9780792377887
- Edition
- 1st Edition
- Seller catalogs
- Science, Technology & Computers
"Synopsis" may belong to another edition of this title.
Synopsis
"About the title" may belong to another edition of this title.
BIBLIOPE by Calvello Books
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