Programmable Reed Solomon Codec Design by Bhaumik Jaydeb (3 results)
Programmable Reed-Solomon Codec: Design And Implementation
Bhaumik, Jaydeb; Das, Anindya Sundar; Bhaumik, Jaydeb; Das, Anindya Sundar
- Softcover
Seller: Revaluation Books, Exeter, United KingdomRevaluation Books
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Paperback. Condition: Brand New. 64 pages. 8.66x5.91x0.15 inches. In Stock.
- Softcover
Seller: preigu, Osnabrück, Germanypreigu
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Taschenbuch. Condition: Neu. Programmable Reed-Solomon Codec | Design and Implementation | Jaydeb Bhaumik (u. a.) | Taschenbuch | 64 S. | Englisch | 2013 | LAP LAMBERT Academic Publishing | EAN 9783659457265 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de… | Anbieter: preigu.
- Softcover
- Print on Demand
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in st…orage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.
