Published by Verlag Unser Wissen, 2024
ISBN 10: 6207349148 ISBN 13: 9786207349142
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: As New. Unread book in perfect condition.
Published by Edizioni Sapienza, 2024
ISBN 10: 6207349172 ISBN 13: 9786207349173
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: As New. Unread book in perfect condition.
Published by Editions Notre Savoir, 2024
ISBN 10: 6207349164 ISBN 13: 9786207349166
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: As New. Unread book in perfect condition.
Published by Edicoes Nosso Conhecimento, 2024
ISBN 10: 6207349199 ISBN 13: 9786207349197
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: As New. Unread book in perfect condition.
Published by LAP LAMBERT Academic Publishing, 2013
ISBN 10: 3659214523 ISBN 13: 9783659214523
Seller: Lucky's Textbooks, Dallas, TX, U.S.A.
Condition: New.
Published by Editions Notre Savoir Apr 2024, 2024
ISBN 10: 6207349164 ISBN 13: 9786207349166
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Französisch.
Published by LAP Lambert Academic Publishing Jun 2017, 2017
ISBN 10: 3330085371 ISBN 13: 9783330085374
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Floating point adders are hard to implement on reconfigurable devices because of complexity of their algorithm. Proposed work describes the implementation of floating point adder using sequential and concurrent processing on reconfigurable hardware. Implementation of floating point adder using sequential processing utilizes less chip area but with significant increase in combinational delay and clock period as compared with concurrent processing. Implementation of floating point adder using concurrent processing on Virtex 4 consumes 7% chip area with a combinational delay of 24.201nsec without offset and 27.891nsec offset delay and implementation of floating point adder on Spartan 2E using concurrent processing utilizes 401 slices with a combinational delay of 56.679nsec and consumes 188908 Kbytes of memory while implementing same on Spartan 2E using sequential processing consumes 52% chip area with a combinational delay of 69.987nsec and it implies that clock speed of concurrent processing is more than sequential processing but area consumption is also more. 72 pp. Englisch.
Published by Verlag Unser Wissen Apr 2024, 2024
ISBN 10: 6207349148 ISBN 13: 9786207349142
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Deutsch.
Published by Ediciones Nuestro Conocimiento Apr 2024, 2024
ISBN 10: 6207349156 ISBN 13: 9786207349159
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Spanisch.
Published by Edições Nosso Conhecimento Apr 2024, 2024
ISBN 10: 6207349199 ISBN 13: 9786207349197
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Portugiesisch.
Published by Edizioni Sapienza Apr 2024, 2024
ISBN 10: 6207349172 ISBN 13: 9786207349173
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Italienisch.
Published by LAP LAMBERT Academic Publishing, 2013
ISBN 10: 3659214523 ISBN 13: 9783659214523
Seller: PBShop.store UK, Fairford, GLOS, United Kingdom
PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
Published by Editions Notre Savoir, 2024
ISBN 10: 6207349164 ISBN 13: 9786207349166
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: New.
Published by Edizioni Sapienza, 2024
ISBN 10: 6207349172 ISBN 13: 9786207349173
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: New.
Published by Verlag Unser Wissen, 2024
ISBN 10: 6207349148 ISBN 13: 9786207349142
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: New.
Published by Edicoes Nosso Conhecimento, 2024
ISBN 10: 6207349199 ISBN 13: 9786207349197
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: New.
Published by LAP Lambert Academic Publishing, 2013
ISBN 10: 3659214523 ISBN 13: 9783659214523
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Condition: New. PRINT ON DEMAND Book; New; Fast Shipping from the UK. No. book.
Published by Editions Notre Savoir, 2024
ISBN 10: 6207349164 ISBN 13: 9786207349166
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: New.
Published by Edicoes Nosso Conhecimento, 2024
ISBN 10: 6207349199 ISBN 13: 9786207349197
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: New.
Published by Edizioni Sapienza, 2024
ISBN 10: 6207349172 ISBN 13: 9786207349173
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: New.
Published by Verlag Unser Wissen, 2024
ISBN 10: 6207349148 ISBN 13: 9786207349142
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: New.
Published by Verlag Unser Wissen, 2024
ISBN 10: 6207349148 ISBN 13: 9786207349142
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: As New. Unread book in perfect condition.
Published by Editions Notre Savoir, 2024
ISBN 10: 6207349164 ISBN 13: 9786207349166
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: As New. Unread book in perfect condition.
Published by Edizioni Sapienza, 2024
ISBN 10: 6207349172 ISBN 13: 9786207349173
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: As New. Unread book in perfect condition.
Published by Edicoes Nosso Conhecimento, 2024
ISBN 10: 6207349199 ISBN 13: 9786207349197
Seller: GreatBookPricesUK, Castle Donington, DERBY, United Kingdom
Condition: As New. Unread book in perfect condition.
Published by LAP Lambert Academic Publishing 2013-01, 2013
ISBN 10: 3659214523 ISBN 13: 9783659214523
Seller: Chiron Media, Wallingford, United Kingdom
PF. Condition: New.
Published by LAP Lambert Academic Publishing, 2017
ISBN 10: 3330085371 ISBN 13: 9783330085374
Seller: AHA-BUCH GmbH, Einbeck, Germany
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Floating point adders are hard to implement on reconfigurable devices because of complexity of their algorithm. Proposed work describes the implementation of floating point adder using sequential and concurrent processing on reconfigurable hardware. Implementation of floating point adder using sequential processing utilizes less chip area but with significant increase in combinational delay and clock period as compared with concurrent processing. Implementation of floating point adder using concurrent processing on Virtex 4 consumes 7% chip area with a combinational delay of 24.201nsec without offset and 27.891nsec offset delay and implementation of floating point adder on Spartan 2E using concurrent processing utilizes 401 slices with a combinational delay of 56.679nsec and consumes 188908 Kbytes of memory while implementing same on Spartan 2E using sequential processing consumes 52% chip area with a combinational delay of 69.987nsec and it implies that clock speed of concurrent processing is more than sequential processing but area consumption is also more.
Published by Verlag Unser Wissen, 2024
ISBN 10: 6207349148 ISBN 13: 9786207349142
Seller: AHA-BUCH GmbH, Einbeck, Germany
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Fließkomma-Addierer sind aufgrund der Komplexität ihres Algorithmus schwer auf rekonfigurierbaren Geräten zu implementieren. Die vorgeschlagene Arbeit beschreibt die Implementierung eines Fließkomma-Addierers mit sequentieller und gleichzeitiger Verarbeitung auf rekonfigurierbarer Hardware. Die Implementierung eines Fließkomma-Addierers mit sequentieller Verarbeitung benötigt weniger Chipfläche, führt aber im Vergleich zur gleichzeitigen Verarbeitung zu einer deutlichen Erhöhung der kombinatorischen Verzögerung und der Taktperiode. Die Implementierung eines Gleitkomma-Addierers mit gleichzeitiger Verarbeitung auf Virtex 4 verbraucht 7% Chipfläche mit einer kombinatorischen Verzögerung von 24,201nsec ohne Offset und 27,891nsec Offset-Verzögerung, während die Implementierung eines Gleitkomma-Addierers auf Spartan 2E mit gleichzeitiger Verarbeitung 401 Slices mit einer kombinatorischen Verzögerung von 56. 679nsec und verbraucht 188908 Kbytes Speicher, während die Implementierung desselben auf Spartan 2E unter Verwendung sequentieller Verarbeitung 52% Chipfläche mit einer kombinatorischen Verzögerung von 69,987nsec verbraucht, was bedeutet, dass die Taktgeschwindigkeit der gleichzeitigen Verarbeitung höher ist als die der sequentiellen Verarbeitung, aber der Flächenverbrauch ist auch höher.
Published by LAP LAMBERT Academic Publishing, 2013
ISBN 10: 3659214523 ISBN 13: 9783659214523
Seller: PBShop.store US, Wood Dale, IL, U.S.A.
PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
Published by Edizioni Sapienza, 2024
ISBN 10: 6207349172 ISBN 13: 9786207349173
Seller: AHA-BUCH GmbH, Einbeck, Germany
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Gli addizionatori in virgola mobile sono difficili da implementare su dispositivi riconfigurabili a causa della complessità del loro algoritmo. Il lavoro proposto descrive l'implementazione di un sommatore in virgola mobile con elaborazione sequenziale e concorrente su hardware riconfigurabile. L'implementazione di un sommatore a virgola mobile con elaborazione sequenziale utilizza una minore area del chip, ma con un aumento significativo del ritardo combinazionale e del periodo di clock rispetto all'elaborazione concorrente. L'implementazione dell'addizionatore in virgola mobile con l'elaborazione concorrente su Virtex 4 consuma il 7% dell'area del chip con un ritardo combinazionale di 24,201nsec senza offset e 27,891nsec con offset, mentre l'implementazione dell'addizionatore in virgola mobile su Spartan 2E con l'elaborazione concorrente utilizza 401 slice con un ritardo combinazionale di 56,679nsec e consuma 188 slice. 679nsec e consuma 188908 Kbyte di memoria, mentre l'implementazione dello stesso su Spartan 2E con l'elaborazione sequenziale consuma il 52% dell'area del chip con un ritardo combinazionale di 69,987nsec; ciò implica che la velocità di clock dell'elaborazione concorrente è superiore a quella dell'elaborazione sequenziale, ma anche il consumo di area è maggiore.