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Implementation of Floating Point Multiplier on Reconfigurable Hardware: Floating Point Multiplier - Softcover
Foating point operations are hard to implement on reconfigurable devices because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore VHDL programming for IEEE single precision floating point multiplier module have been explored. Various parameters i.e. combinational delay (Latency), chip area (number of slices used), modeling formats, memory usage etc have been analyzed while implementing the floating point multiplier on reconfigurable hardware. Analyzing the various parameters will provide with the information that Vertex4 will consume less chip Area i.e. 663 with reduced latency i.e. 49.906 ns as compared with the other FPGAs i.e. Spartan 2, Spartan 2E, Spartan 3, Spartan 3E, Virtex, Virtex 2, Virtex 2P, and Virtex E. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed.
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About the Author:
Er. Karan Gumber has completed my Master of Engineering from University Institute of Engineering and technology, Panjab University in Electronics and communication. Thesis work of M.E is pursuing under the guidance of Sharmelee Thangjam.
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- PublisherLAP LAMBERT Academic Publishing
- Publication date2013
- ISBN 10 3659214523
- ISBN 13 9783659214523
- BindingPaperback
- Number of pages104
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Implementation of Floating Point Multiplier on Reconfigurable Hardware: Floating Point Multiplier
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Implementation of Floating Point Multiplier on Reconfigurable Hardware
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Book Description Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Foating point operations are hard to implement on reconfigurable devices because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore VHDL programming for IEEE single precision floating point multiplier module have been explored. Various parameters i.e. combinational delay (Latency), chip area (number of slices used), modeling formats, memory usage etc have been analyzed while implementing the floating point multiplier on reconfigurable hardware. Analyzing the various parameters will provide with the information that Vertex4 will consume less chip Area i.e. 663 with reduced latency i.e. 49.906 ns as compared with the other FPGAs i.e. Spartan 2, Spartan 2E, Spartan 3, Spartan 3E, Virtex, Virtex 2, Virtex 2P, and Virtex E. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed. 104 pp. Englisch. Seller Inventory # 9783659214523
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Implementation of Floating Point Multiplier on Reconfigurable Hardware : Floating Point Multiplier
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Book Description Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Foating point operations are hard to implement on reconfigurable devices because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore VHDL programming for IEEE single precision floating point multiplier module have been explored. Various parameters i.e. combinational delay (Latency), chip area (number of slices used), modeling formats, memory usage etc have been analyzed while implementing the floating point multiplier on reconfigurable hardware. Analyzing the various parameters will provide with the information that Vertex4 will consume less chip Area i.e. 663 with reduced latency i.e. 49.906 ns as compared with the other FPGAs i.e. Spartan 2, Spartan 2E, Spartan 3, Spartan 3E, Virtex, Virtex 2, Virtex 2P, and Virtex E. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed. Seller Inventory # 9783659214523
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Implementation of Floating Point Multiplier on Reconfigurable Hardware
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Book Description Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Gumber KaranEr. Karan Gumber has completed my Master of Engineering from University Institute of Engineering and technology, Panjab University in Electronics and communication. Thesis work of M.E is pursuing under the guidance of Sh. Seller Inventory # 5140272
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