Writing Testbenches: Functional Verification of HDL Models

Bergeron, Janick

ISBN 10: 0792377664 / ISBN 13: 9780792377665

Published by Springer, 2000

About this Item

Seller Inventory # Abebooks235067

Bibliographic Details

• Title: Writing Testbenches: Functional Verification of HDL Models
• Publisher: Springer
• Publication Date: 2000
• Language: English
• ISBN 10: 0792377664
• ISBN 13: 9780792377665
• Binding: Hardcover
• Condition: New

About this title

Synopsis

This text first introduces the necessary concepts and tools of verification, then describes a process for carrying out an effective functional verification of a design. This book also presents techniques for applying a stimulus and monitoring the response of a design by abstracting the operations using bus-functional models. The architecture of testbenches built around these bus-functional models is important for minimizing development and maintenance effort. Behavioural modelling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioural modelling is synonymous with synthesizeable or RTL modelling. In this book, the term "behavioural" is used to describe any model that adequately emulates the functionality of a design, usually using non-synthesizeable constructs and coding style. The text focuses on the functional verification of hardware designs using either VHDL or Verilog. The reader should have at least a basic knowledge of one of the languages. Ideally, he or she should have experience in writing synthesizeable models and be familiar with running a simulation using any of the available VHDL or Verilog simulators.

Review

"Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition..."
(Grant Martin, Fellow, Cadence Berkeley Labs)
"In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem..."
(Chris Macinonski, Senior Engineer, Qualis Design Corp.)
"Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification..."
(Brian Bailey, Chief Technologist, Mentor Graphics Corp.)
"A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process."
(Ben Cohen, VhdlCohen Training)