For introductory-level courses in Verilog Hardware Description Language. Written by the co-developer of the Verilog Implicit To One hot (VITO) preprocessor, this text introduces the industry standard Verilog Hardware Description Language as a new way to explore enduring concepts in digital and computer design, such as pipelining. It shows how Verilog simulation is a tool for uncovering bugs prior to hardware fabrication, and how Verilog synthesis is a tool for automatically converting source code into hardware. Ideal for designers new to Verilog, it features a consistent design framework using ASM charts, and contains many realistic, practical examples.

About the Author

MARK GORDON ARNOLD has taught Verilog at the University of Wyoming in Laramie, Wyoming since 1993, and is co-author of several papers on Verilog computer design, including "A Synthesis Preprocessor That Converts Implicit Style Verilog Into One-Hot De signs," winner of the Best Paper Award at the 1997 International Verilog Conference. Arnold holds three patents.

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