Verification Methodology Manual: Techniques for Verifying HDL Designs - Second Edition

Dempster, David John; Stuart, Michael George

ISBN 10: 0953848213 / ISBN 13: 9780953848218

Published by Teamwork International, Yateley, United Kingdom, 2001

About this Item

2nd Edition. Pictorial glazed bds. Rub to spine ends and corners. Prev owners name to fep. Interior Excellent. Very good, clean condition. Seller Inventory # 038014

Bibliographic Details

Title: Verification Methodology Manual: Techniques ...

Publisher: Teamwork International, Yateley, United Kingdom

Publication Date: 2001

Binding: Hard Cover

Illustrator: Chris Moses

Condition: Very Good

Dust Jacket Condition: No Jacket

Edition: 2nd Edition

About this title

Synopsis:

This manual has been specifically written for hardware designers that use the Verilog or VHDL hardware description languages to design complex integrated circuits. Whether a designer designs individual circuit modules or complete systems, designers are always faced with the problem of ensuring that the final design is completely free of errors. Achieving design-quality while satisfying budget and time constraints is one of the major objectives for designers in the 21st century. The manual lays the foundation for a methodology based on the effective use of the following front-end design tools and validation techniques. Code and rule checking; Coverage analysis; Test suite analysis; Pre-silicon validation; The manual includes numerous examples of front-end verification techniques using leading-edge HDL verification tools supplied by TransEDA (one of the world's foremost EDA tool vendors). The manual contains a number of case studies and worked examples that together with evaluation copies of TransEDA's verification tools may be downloaded from the World Wide Web for evaluation purposes.